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Message-ID: <20250903094235875lEi-uxy_pNfW8n_1JvFVr@zte.com.cn>
Date: Wed, 3 Sep 2025 09:42:35 +0800 (CST)
From: <liu.xuemei1@....com.cn>
To: <alex@...ti.fr>, <paul.walmsley@...ive.com>
Cc: <palmer@...belt.com>, <aou@...s.berkeley.edu>, <spersvold@...il.com>,
        <sudeep.holla@....com>, <mikisabate@...il.com>, <robh@...nel.org>,
        <liu.xuemei1@....com.cn>, <linux-riscv@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] riscv: cacheinfo: init cache levels via fetch_cache_info when SMP disabled

>> Hi Jessica,
>>
>> On 8/14/25 03:29, liu.xuemei1@....com.cn wrote:
>>>
>>> Hi Alex,
>>>
>>>
>>> >> Hi Jessica,
>>>
>>> >>
>>>
>>> >> On 8/1/25 03:32, liu.xuemei1@....com.cn wrote:
>>>
>>> >>>
>>>
>>> >>> On 7/31/25 21:29, alex@...ti.fr wrote:
>>>
>>> >>>
>>>
>>> >>> > > From: Jessica Liu <liu.xuemei1@....com.cn>
>>>
>>> >>>
>>>
>>> >>> > >
>>>
>>> >>>
>>>
>>> >>> > > As described in commit 1845d381f280 ("riscv: cacheinfo: Add back
>>>
>>> >>>
>>>
>>> >>> > > init_cache_level() function"), when CONFIG_SMP is undefined, the
>>>
>>> >>> cache
>>>
>>> >>>
>>>
>>> >>> > > hierarchy detection needs to be performed through the
>>>
>>> >>> init_cache_level(),
>>>
>>> >>>
>>>
>>> >>> > > whereas when CONFIG_SMP is defined, this detection is handled
>>>
>>> >>> during the
>>>
>>> >>>
>>>
>>> >>> > > init_cpu_topology() process.
>>>
>>> >>>
>>>
>>> >>> > >
>>>
>>> >>>
>>>
>>> >>> > > Furthermore, while commit 66381d36771e ("RISC-V: Select ACPI 
>>> PPTT
>>>
>>> >>> drivers")
>>>
>>> >>>
>>>
>>> >>> > > enables cache information retrieval through the ACPI PPTT 
>>> table, the
>>>
>>> >>>
>>>
>>> >>> > > init_of_cache_level() called within init_cache_level() cannot
>>>
>>> >>> support cache
>>>
>>> >>>
>>>
>>> >>> > > hierarchy detection through ACPI PPTT. Therefore, when 
>>> CONFIG_SMP is
>>>
>>> >>>
>>>
>>> >>> > > undefined, we directly invoke the fetch_cache_info function to
>>>
>>> >>> initialize
>>>
>>> >>>
>>>
>>> >>> > > the cache levels.
>>>
>>> >>>
>>>
>>> >>> > >
>>>
>>> >>>
>>>
>>> >>> > > Signed-off-by: Jessica Liu <liu.xuemei1@....com.cn>
>>>
>>> >>>
>>>
>>> >>> > > ---
>>>
>>> >>>
>>>
>>> >>> > >   arch/riscv/kernel/cacheinfo.c | 6 +++++-
>>>
>>> >>>
>>>
>>> >>> > >   1 file changed, 5 insertions(+), 1 deletion(-)
>>>
>>> >>>
>>>
>>> >>> > >
>>>
>>> >>>
>>>
>>> >>> > > diff --git a/arch/riscv/kernel/cacheinfo.c
>>>
>>> >>> b/arch/riscv/kernel/cacheinfo.c
>>>
>>> >>>
>>>
>>> >>> > > index 26b085dbdd07..f81ca963d177 100644
>>>
>>> >>>
>>>
>>> >>> > > --- a/arch/riscv/kernel/cacheinfo.c
>>>
>>> >>>
>>>
>>> >>> > > +++ b/arch/riscv/kernel/cacheinfo.c
>>>
>>> >>>
>>>
>>> >>> > > @@ -73,7 +73,11 @@ static void ci_leaf_init(struct cacheinfo
>>>
>>> >>> *this_leaf,
>>>
>>> >>>
>>>
>>> >>> > >
>>>
>>> >>>
>>>
>>> >>> > >   int init_cache_level(unsigned int cpu)
>>>
>>> >>>
>>>
>>> >>> > >   {
>>>
>>> >>>
>>>
>>> >>> > > -    return init_of_cache_level(cpu);
>>>
>>> >>>
>>>
>>> >>> > > +#ifdef CONFIG_SMP
>>>
>>> >>>
>>>
>>> >>> > > +    return 0;
>>>
>>> >>>
>>>
>>> >>> > > +#endif
>>>
>>> >>>
>>>
>>> >>> > > +
>>>
>>> >>>
>>>
>>> >>> > > +    return fetch_cache_info(cpu);
>>>
>>> >>>
>>>
>>> >>> > >   }
>>>
>>> >>>
>>>
>>> >>> > >
>>>
>>> >>>
>>>
>>> >>> > >   int populate_cache_leaves(unsigned int cpu)
>>>
>>> >>>
>>>
>>> >>> >
>>>
>>> >>>
>>>
>>> >>> >
>>>
>>> >>>
>>>
>>> >>> > Is the current behaviour wrong or just redundant? If wrong, 
>>> I'll add a
>>>
>>> >>>
>>>
>>> >>> > Fixes tag to backport, otherwise I won't.
>>>
>>> >>>
>>>
>>> >>> >
>>>
>>> >>>
>>>
>>> >>> > Thanks,
>>>
>>> >>>
>>>
>>> >>> >
>>>
>>> >>>
>>>
>>> >>> > Alex
>>>
>>> >>>
>>>
>>> >>>
>>>
>>> >>> Hi Alex,
>>>
>>> >>>
>>>
>>> >>>
>>>
>>> >>> The current behavior is actually wrong when using ACPI on 
>>> !CONFIG_SMP
>>>
>>> >>>
>>>
>>> >>> systems. The original init_of_cache_level() cannot detect cache
>>>
>>> >>> hierarchy
>>>
>>> >>>
>>>
>>> >>> through ACPI PPTT table, which means cache information would be 
>>> missing
>>>
>>> >>>
>>>
>>> >>> in this configuration.
>>>
>>> >>>
>>>
>>> >>>
>>>
>>> >>> The patch fixes this by directly calling fetch_cache_info() when
>>>
>>> >>>
>>>
>>> >>> CONFIG_SMP is undefined, which properly handles both DT and ACPI 
>>> cases..
>>>
>>> >>>
>>>
>>> >>>
>>>
>>> >>> So yes, it would be appropriate to add a Fixes tag. The commit being
>>>
>>> >>>
>>>
>>> >>> fixed is 1845d381f280 ("riscv: cacheinfo: Add back 
>>> init_cache_level()
>>>
>>> >>> function").
>>>
>>> >>>
>>>
>>> >>>
>>>
>>> >>> Please let me know if you need any additional information.
>>>
>>> >>>
>>>
>>> >>
>>>
>>> >> I'm about to send my first PR for 6.17 so I'll delay merging this one
>>>
>>> >> for the first rc.
>>>
>>> >
>>>
>>> >
>>>
>>> >So I took the time this morning to look into this, and I don't really
>>>
>>> >like the different treatment for smp, can't we just move
>>>
>>> >init_cpu_topology() call to setup_arch() (or else) for both !smp and 
>>> smp?
>>>
>>> >
>>>
>>> >Thanks,
>>>
>>> >
>>>
>>> >Alex
>>>
>>>
>>> Thank you for your feedback and suggestion. I understand your desire
>>>
>>> to have a unified approach for both SMP and !SMP. However, after
>>>
>>> careful consideration, I still believe that handling them separately
>>>
>>> is the more appropriate solution.
>>>
>>>
>>> The current method of obtaining cache information in
>>>
>>> `init_cpu_topology()` is specific to RISC-V and ARM64. If we move
>>>
>>> `init_cpu_topology()` to cover both SMP and !SMP, it may require
>>>
>>> modifying the generic boot sequence. This could inadvertently affect
>>>
>>> other architectures that do not rely on `init_cpu_topology()` for
>>>
>>> cache initialization, leading to potential regressions and maintenance
>>>
>>> issues.
>>>
>>>
>>> The `setup_arch()` function is called early in the boot process,
>>>
>>> and at this stage, the ACPI subsystem has not been fully initialized.
>>>
>>> Specifically, the ACPI tables (including PPTT) are not yet parsed.
>>>
>>> Therefore, if we call `init_cpu_topology()` from `setup_arch()`, it
>>>
>>> would not be able to retrieve cache information from the ACPI PPTT 
>>> table.
>>>
>>>
>>> I hope this clarifies my train of thought. I'm open to further 
>>> discussion and
>>>
>>> alternative suggestions that can address the issue properly.
>>>
>>
>> To me it does not make sense to retrieve the cache info at 2 different 
>> points in time if the system is smp or not. I still think we should 
>> find a common place where init_cpu_topology() can be called for both 
>> smp and up, setup_arch() could not be the right place for the reasons 
>> you gave, but we just need to find the right one :)
>>
>> Thanks for working on this,
>
>
>I don't mean to pressure you, I know it's the end of summer and people 
>are still on vacations or just back from vacation.
>
>I just wanted to know if you had time to look into what I asked above?
>
>Thanks,
>
>Alex

Hi Alex,

Thank you for the reminder, and I hope you had a good summer. I did just
returned from vacation.

I understand your concern about having a unified approach for cache
initialization in both SMP and !SMP configurations. I will look into your
suggestion carefully. Once I have a solution, I will test it thoroughly
and send a revised patch.

I appreciate your patience and guidance.

Best regards,
Jessica
>
>
>>
>> Alex
>>
>>
>>>
>>> Best regards,
>>>
>>> Jessica
<div class="zcontentRow"><p>&gt;&gt; Hi Jessica,</p><p>&gt;&gt;</p><p>&gt;&gt; On 8/14/25 03:29, liu.xuemei1@....com.cn wrote:</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; Hi Alex,</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt; Hi Jessica,</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt; On 8/1/25 03:32, liu.xuemei1@....com.cn wrote:</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; On 7/31/25 21:29, alex@...ti.fr wrote:</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt; From: Jessica Liu &lt;liu.xuemei1@....com.cn&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt; As described in commit 1845d381f280 ("riscv: cacheinfo: Add back</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt; init_cache_level() function"), when CONFIG_SMP is undefined, the</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; cache</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt; hierarchy detection needs to be performed through the</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; init_cache_level(),</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt; whereas when CONFIG_SMP is defined, this detection is handled</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; during the</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt; init_cpu_topology() process.</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt; Furthermore, while commit 66381d36771e ("RISC-V: Select ACPI&nbsp;</p><p>&gt;&gt;&gt; PPTT</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; drivers")</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt; enables cache information retrieval through the ACPI PPTT&nbsp;</p><p>&gt;&gt;&gt; table, the</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt; init_of_cache_level() called within init_cache_level() cannot</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; support cache</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt; hierarchy detection through ACPI PPTT. Therefore, when&nbsp;</p><p>&gt;&gt;&gt; CONFIG_SMP is</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt; undefined, we directly invoke the fetch_cache_info function to</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; initialize</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt; the cache levels.</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt; Signed-off-by: Jessica Liu &lt;liu.xuemei1@....com.cn&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt; ---</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt;&nbsp; &nbsp;arch/riscv/kernel/cacheinfo.c | 6 +++++-</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt;&nbsp; &nbsp;1 file changed, 5 insertions(+), 1 deletion(-)</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt; diff --git a/arch/riscv/kernel/cacheinfo.c</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; b/arch/riscv/kernel/cacheinfo.c</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt; index 26b085dbdd07..f81ca963d177 100644</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt; --- a/arch/riscv/kernel/cacheinfo.c</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt; +++ b/arch/riscv/kernel/cacheinfo.c</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt; @@ -73,7 +73,11 @@ static void ci_leaf_init(struct cacheinfo</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; *this_leaf,</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt;&nbsp; &nbsp;int init_cache_level(unsigned int cpu)</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt;&nbsp; &nbsp;{</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt; -&nbsp; &nbsp; return init_of_cache_level(cpu);</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt; +#ifdef CONFIG_SMP</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt; +&nbsp; &nbsp; return 0;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt; +#endif</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt; +</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt; +&nbsp; &nbsp; return fetch_cache_info(cpu);</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt;&nbsp; &nbsp;}</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; &gt;&nbsp; &nbsp;int populate_cache_leaves(unsigned int cpu)</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; Is the current behaviour wrong or just redundant? If wrong,&nbsp;</p><p>&gt;&gt;&gt; I'll add a</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; Fixes tag to backport, otherwise I won't.</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; Thanks,</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; &gt; Alex</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; Hi Alex,</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; The current behavior is actually wrong when using ACPI on&nbsp;</p><p>&gt;&gt;&gt; !CONFIG_SMP</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; systems. The original init_of_cache_level() cannot detect cache</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; hierarchy</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; through ACPI PPTT table, which means cache information would be&nbsp;</p><p>&gt;&gt;&gt; missing</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; in this configuration.</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; The patch fixes this by directly calling fetch_cache_info() when</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; CONFIG_SMP is undefined, which properly handles both DT and ACPI&nbsp;</p><p>&gt;&gt;&gt; cases..</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; So yes, it would be appropriate to add a Fixes tag. The commit being</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; fixed is 1845d381f280 ("riscv: cacheinfo: Add back&nbsp;</p><p>&gt;&gt;&gt; init_cache_level()</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; function").</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt; Please let me know if you need any additional information.</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt; I'm about to send my first PR for 6.17 so I'll delay merging this one</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;&gt; for the first rc.</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;So I took the time this morning to look into this, and I don't really</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;like the different treatment for smp, can't we just move</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;init_cpu_topology() call to setup_arch() (or else) for both !smp and&nbsp;</p><p>&gt;&gt;&gt; smp?</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;Thanks,</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; &gt;Alex</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; Thank you for your feedback and suggestion. I understand your desire</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; to have a unified approach for both SMP and !SMP. However, after</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; careful consideration, I still believe that handling them separately</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; is the more appropriate solution.</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; The current method of obtaining cache information in</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; `init_cpu_topology()` is specific to RISC-V and ARM64. If we move</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; `init_cpu_topology()` to cover both SMP and !SMP, it may require</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; modifying the generic boot sequence. This could inadvertently affect</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; other architectures that do not rely on `init_cpu_topology()` for</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; cache initialization, leading to potential regressions and maintenance</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; issues.</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; The `setup_arch()` function is called early in the boot process,</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; and at this stage, the ACPI subsystem has not been fully initialized.</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; Specifically, the ACPI tables (including PPTT) are not yet parsed.</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; Therefore, if we call `init_cpu_topology()` from `setup_arch()`, it</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; would not be able to retrieve cache information from the ACPI PPTT&nbsp;</p><p>&gt;&gt;&gt; table.</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; I hope this clarifies my train of thought. I'm open to further&nbsp;</p><p>&gt;&gt;&gt; discussion and</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; alternative suggestions that can address the issue properly.</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;</p><p>&gt;&gt; To me it does not make sense to retrieve the cache info at 2 different&nbsp;</p><p>&gt;&gt; points in time if the system is smp or not. I still think we should&nbsp;</p><p>&gt;&gt; find a common place where init_cpu_topology() can be called for both&nbsp;</p><p>&gt;&gt; smp and up, setup_arch() could not be the right place for the reasons&nbsp;</p><p>&gt;&gt; you gave, but we just need to find the right one :)</p><p>&gt;&gt;</p><p>&gt;&gt; Thanks for working on this,</p><p>&gt;</p><p>&gt;</p><p>&gt;I don't mean to pressure you, I know it's the end of summer and people&nbsp;</p><p>&gt;are still on vacations or just back from vacation.</p><p>&gt;</p><p>&gt;I just wanted to know if you had time to look into what I asked above?</p><p>&gt;</p><p>&gt;Thanks,</p><p>&gt;</p><p>&gt;Alex</p><p><br></p><p>Hi Alex,</p><p><br></p><p>Thank you for the reminder, and I hope you had a good summer. I did just</p><p>returned from vacation.</p><p><br></p><p>I understand your concern about having a unified approach for cache</p><p>initialization in both SMP and !SMP configurations. I will look into your</p><p>suggestion carefully. Once I have a solution, I will test it thoroughly</p><p>and send a revised patch.</p><p><br></p><p>I appreciate your patience and guidance.</p><p><br></p><p>Best regards,</p><p>Jessica</p><p>&gt;</p><p>&gt;</p><p>&gt;&gt;</p><p>&gt;&gt; Alex</p><p>&gt;&gt;</p><p>&gt;&gt;</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; Best regards,</p><p>&gt;&gt;&gt;</p><p>&gt;&gt;&gt; Jessica</p><p style="font-size:14px;font-family:微软雅黑,Microsoft YaHei;"><br></p><p style="font-size:14px;font-family:微软雅黑,Microsoft YaHei;"><br></p><p style="font-size:14px;font-family:微软雅黑,Microsoft YaHei;"><br></p><p style="font-size:14px;font-family:微软雅黑,Microsoft YaHei;"><br></p><p><br></p></div>

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