linux-kernel - Re: [PATCH net] net: stmmac: dwmac-rk: Ensure clk

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <aLly7lJ05xQjqCWn@shell.armlinux.org.uk>
Date: Thu, 4 Sep 2025 12:07:26 +0100
From: "Russell King (Oracle)" <linux@...linux.org.uk>
To: Chaoyi Chen <chaoyi.chen@...k-chips.com>
Cc: Yao Zi <ziyao@...root.org>, Andrew Lunn <andrew+netdev@...n.ch>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Jonas Karlman <jonas@...boo.se>, David Wu <david.wu@...k-chips.com>,
	netdev@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org, linux-rockchip@...ts.infradead.org
Subject: Re: [PATCH net] net: stmmac: dwmac-rk: Ensure clk_phy doesn't
 contain invalid address

On Thu, Sep 04, 2025 at 12:05:19PM +0100, Russell King (Oracle) wrote:
> On Thu, Sep 04, 2025 at 07:03:10PM +0800, Chaoyi Chen wrote:
> > 
> > On 9/4/2025 6:58 PM, Russell King (Oracle) wrote:
> > > On Thu, Sep 04, 2025 at 03:12:24AM +0000, Yao Zi wrote:
> > > >   	if (plat->phy_node) {
> > > >   		bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0);
> > > >   		ret = PTR_ERR_OR_ZERO(bsp_priv->clk_phy);
> > > > -		/* If it is not integrated_phy, clk_phy is optional */
> > > > +		/*
> > > > +		 * If it is not integrated_phy, clk_phy is optional. But we must
> > > > +		 * set bsp_priv->clk_phy to NULL if clk_phy isn't proivded, or
> > > > +		 * the error code could be wrongly taken as an invalid pointer.
> > > > +		 */
> > > I'm concerned by this. This code is getting the first clock from the DT
> > > description of the PHY. We don't know what type of PHY it is, or what
> > > the DT description of that PHY might suggest that the first clock would
> > > be.
> > > 
> > > However, we're geting it and setting it to 50MHz. What if the clock is
> > > not what we think it is?
> > 
> > We only set integrated_phy to 50M, which are all known targets. For external PHYs, we do not perform frequency settings.
> 
> Same question concerning enabling and disabling another device's clock
> that the other device should be handling.

Let me be absolutely clear: I consider *everything* that is going on
with clk_phy here to be a dirty hack.

Resources used by a device that has its own driver should be managed
by _that_ driver alone, not by some other random driver.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!