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Message-Id: <20250904-topic-cci_updates-v1-1-d38559692703@oss.qualcomm.com>
Date: Thu, 04 Sep 2025 16:31:20 +0200
From: Konrad Dybcio <konradybcio@...nel.org>
To: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Bryan O'Donoghue <bryan.odonoghue@...aro.org>,
Loic Poulain <loic.poulain@....qualcomm.com>,
Robert Foss <rfoss@...nel.org>, Andi Shyti <andi.shyti@...nel.org>
Cc: Marijn Suijten <marijn.suijten@...ainline.org>,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-i2c@...r.kernel.org,
Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: [PATCH 1/5] arm64: dts: qcom: sc8280xp: Fix CCI3 interrupt
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
This was evidently wrong, as exemplified by the core failing to reset
at probe (which would be completed by the IRQ firing).
Fix it.
Fixes: 7cfa2e758bf4 ("arm64: dts: qcom: sc8280xp: camss: Add CCI definitions")
Signed-off-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 225233a37a4fd9f3d65735915c0338a993a322d1..18b5cb441f955f7a91204376e05536b203f3e28b 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -4292,7 +4292,7 @@ cci3: cci@...d000 {
compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
reg = <0 0x0ac4d000 0 0x1000>;
- interrupts = <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>;
clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
<&camcc CAMCC_SLOW_AHB_CLK_SRC>,
--
2.51.0
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