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Message-Id: <20250904-topic-cci_updates-v1-5-d38559692703@oss.qualcomm.com>
Date: Thu, 04 Sep 2025 16:31:24 +0200
From: Konrad Dybcio <konradybcio@...nel.org>
To: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Bryan O'Donoghue <bryan.odonoghue@...aro.org>,
Loic Poulain <loic.poulain@....qualcomm.com>,
Robert Foss <rfoss@...nel.org>, Andi Shyti <andi.shyti@...nel.org>
Cc: Marijn Suijten <marijn.suijten@...ainline.org>,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-i2c@...r.kernel.org,
Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: [PATCH 5/5] arm64: dts: qcom: sc8280xp: Add OPP table for CCI
hosts
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
The CCI hosts have both frequency and voltage requirements (which
happen to be common across instances on a given SoC, at least so far).
Express them by introducing an OPP table and linking it to the hosts.
Signed-off-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 18b5cb441f955f7a91204376e05536b203f3e28b..c396186317d49f411d7162771a358563329a02a4 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -391,6 +391,15 @@ memory@...00000 {
reg = <0x0 0x80000000 0x0 0x0>;
};
+ cci_opp_table: opp-table-cci {
+ compatible = "operating-points-v2";
+
+ opp-37500000 {
+ opp-hz = /bits/ 64 <37500000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+ };
+
cpu0_opp_table: opp-table-cpu0 {
compatible = "operating-points-v2";
opp-shared;
@@ -4181,6 +4190,7 @@ cci0: cci@...a000 {
"cpas_ahb",
"cci";
+ operating-points-v2 = <&cci_opp_table>;
power-domains = <&camcc TITAN_TOP_GDSC>;
pinctrl-0 = <&cci0_default>;
@@ -4222,6 +4232,7 @@ cci1: cci@...b000 {
"cpas_ahb",
"cci";
+ operating-points-v2 = <&cci_opp_table>;
power-domains = <&camcc TITAN_TOP_GDSC>;
pinctrl-0 = <&cci1_default>;
@@ -4262,6 +4273,8 @@ cci2: cci@...c000 {
"slow_ahb_src",
"cpas_ahb",
"cci";
+
+ operating-points-v2 = <&cci_opp_table>;
power-domains = <&camcc TITAN_TOP_GDSC>;
pinctrl-0 = <&cci2_default>;
@@ -4303,6 +4316,7 @@ cci3: cci@...d000 {
"cpas_ahb",
"cci";
+ operating-points-v2 = <&cci_opp_table>;
power-domains = <&camcc TITAN_TOP_GDSC>;
pinctrl-0 = <&cci3_default>;
--
2.51.0
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