| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20250904154402.300032-12-vladimir.oltean@nxp.com>
Date: Thu, 4 Sep 2025 18:43:59 +0300
From: Vladimir Oltean <vladimir.oltean@....com>
To: linux-phy@...ts.infradead.org
Cc: Ioana Ciornei <ioana.ciornei@....com>,
Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
linux-kernel@...r.kernel.org
Subject: [PATCH phy 11/14] phy: lynx-28g: truly power the lanes up or down
The current procedure for power_off() and power_on() is the same as the
one used for major lane reconfiguration, aka halting. But one can
observe that a halted lane does not cause, for example, the CDR loop of
the link partner to lose lock on its RX stream.
Implement the procedure mentioned in the block guide for powering down
a lane, and then back on.
Signed-off-by: Vladimir Oltean <vladimir.oltean@....com>
---
drivers/phy/freescale/phy-fsl-lynx-28g.c | 78 ++++++++++++++++++------
1 file changed, 60 insertions(+), 18 deletions(-)
diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
index 08553ffe273f..5055ddba0363 100644
--- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
+++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
@@ -73,9 +73,11 @@
/* Lane a Tx Reset Control Register */
#define LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20)
-#define LNaTRSTCTL_HLT_REQ BIT(27)
-#define LNaTRSTCTL_RST_DONE BIT(30)
#define LNaTRSTCTL_RST_REQ BIT(31)
+#define LNaTRSTCTL_RST_DONE BIT(30)
+#define LNaTRSTCTL_HLT_REQ BIT(27)
+#define LNaTRSTCTL_STP_REQ BIT(26)
+#define LNaTRSTCTL_DIS BIT(24)
/* Lane a Tx General Control Register */
#define LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24)
@@ -102,9 +104,11 @@
/* Lane a Rx Reset Control Register */
#define LNaRRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x40)
-#define LNaRRSTCTL_HLT_REQ BIT(27)
-#define LNaRRSTCTL_RST_DONE BIT(30)
#define LNaRRSTCTL_RST_REQ BIT(31)
+#define LNaRRSTCTL_RST_DONE BIT(30)
+#define LNaRRSTCTL_HLT_REQ BIT(27)
+#define LNaRRSTCTL_STP_REQ BIT(26)
+#define LNaRRSTCTL_DIS BIT(24)
#define LNaRRSTCTL_CDR_LOCK BIT(12)
/* Lane a Rx General Control Register */
@@ -660,14 +664,12 @@ static void lynx_28g_lane_set_pll(struct lynx_28g_lane *lane,
}
}
-static int lynx_28g_power_off(struct phy *phy)
+/* Halting puts the lane in a mode in which it can be reconfigured */
+static void lynx_28g_lane_halt(struct phy *phy)
{
struct lynx_28g_lane *lane = phy_get_drvdata(phy);
u32 trstctl, rrstctl;
- if (!lane->powered_up)
- return 0;
-
/* Issue a halt request */
lynx_28g_lane_rmw(lane, LNaTRSTCTL, LNaTRSTCTL_HLT_REQ,
LNaTRSTCTL_HLT_REQ);
@@ -680,20 +682,13 @@ static int lynx_28g_power_off(struct phy *phy)
rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
} while ((trstctl & LNaTRSTCTL_HLT_REQ) ||
(rrstctl & LNaRRSTCTL_HLT_REQ));
-
- lane->powered_up = false;
-
- return 0;
}
-static int lynx_28g_power_on(struct phy *phy)
+static void lynx_28g_lane_reset(struct phy *phy)
{
struct lynx_28g_lane *lane = phy_get_drvdata(phy);
u32 trstctl, rrstctl;
- if (lane->powered_up)
- return 0;
-
/* Issue a reset request on the lane */
lynx_28g_lane_rmw(lane, LNaTRSTCTL, LNaTRSTCTL_RST_REQ,
LNaTRSTCTL_RST_REQ);
@@ -706,6 +701,52 @@ static int lynx_28g_power_on(struct phy *phy)
rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
} while (!(trstctl & LNaTRSTCTL_RST_DONE) ||
!(rrstctl & LNaRRSTCTL_RST_DONE));
+}
+
+static int lynx_28g_power_off(struct phy *phy)
+{
+ struct lynx_28g_lane *lane = phy_get_drvdata(phy);
+ u32 trstctl, rrstctl;
+
+ if (!lane->powered_up)
+ return 0;
+
+ /* Issue a stop request */
+ lynx_28g_lane_rmw(lane, LNaTRSTCTL, LNaTRSTCTL_STP_REQ,
+ LNaTRSTCTL_STP_REQ);
+ lynx_28g_lane_rmw(lane, LNaRRSTCTL, LNaRRSTCTL_STP_REQ,
+ LNaRRSTCTL_STP_REQ);
+
+ /* Wait until the stop process is complete */
+ do {
+ trstctl = lynx_28g_lane_read(lane, LNaTRSTCTL);
+ rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
+ } while ((trstctl & LNaTRSTCTL_STP_REQ) ||
+ (rrstctl & LNaRRSTCTL_STP_REQ));
+
+ /* Power down the RX and TX portions of the lane */
+ lynx_28g_lane_rmw(lane, LNaRRSTCTL, LNaRRSTCTL_DIS,
+ LNaRRSTCTL_DIS);
+ lynx_28g_lane_rmw(lane, LNaTRSTCTL, LNaTRSTCTL_DIS,
+ LNaTRSTCTL_DIS);
+
+ lane->powered_up = false;
+
+ return 0;
+}
+
+static int lynx_28g_power_on(struct phy *phy)
+{
+ struct lynx_28g_lane *lane = phy_get_drvdata(phy);
+
+ if (lane->powered_up)
+ return 0;
+
+ /* Power up the RX and TX portions of the lane */
+ lynx_28g_lane_rmw(lane, LNaRRSTCTL, 0, LNaRRSTCTL_DIS);
+ lynx_28g_lane_rmw(lane, LNaTRSTCTL, 0, LNaTRSTCTL_DIS);
+
+ lynx_28g_lane_reset(phy);
lane->powered_up = true;
@@ -1035,7 +1076,7 @@ static int lynx_28g_set_mode(struct phy *phy, enum phy_mode mode, int submode)
* the reconfiguration is being done.
*/
if (powered_up)
- lynx_28g_power_off(phy);
+ lynx_28g_lane_halt(phy);
err = lynx_28g_lane_disable_pcvt(lane, lane->mode);
if (err)
@@ -1048,8 +1089,9 @@ static int lynx_28g_set_mode(struct phy *phy, enum phy_mode mode, int submode)
lane->mode = lane_mode;
out:
+ /* Reset the lane if necessary */
if (powered_up)
- lynx_28g_power_on(phy);
+ lynx_28g_lane_reset(phy);
return err;
}
--
2.34.1
Powered by blists - more mailing lists