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Message-ID: <CACRpkdZJ16O+t87aB6dVm7kqCNkiFQiExDVjRJCRgNUhDbzV4w@mail.gmail.com>
Date: Thu, 4 Sep 2025 21:44:31 +0200
From: Linus Walleij <linus.walleij@...aro.org>
To: Yao Zi <ziyao@...root.org>
Cc: Yinbo Zhu <zhuyinbo@...ngson.cn>, Bartosz Golaszewski <brgl@...ev.pl>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Huacai Chen <chenhuacai@...nel.org>, WANG Xuerui <kernel@...0n.name>, 
	Philipp Zabel <p.zabel@...gutronix.de>, linux-gpio@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	loongarch@...ts.linux.dev, Mingcong Bai <jeffbai@...c.io>, 
	Kexy Biscuit <kexybiscuit@...c.io>, Huacai Chen <chenhuacai@...ngson.cn>
Subject: Re: [PATCH v3 2/3] gpio: loongson-64bit: Add support for
 Loongson-2K0300 SoC

On Thu, Sep 4, 2025 at 3:35 AM Yao Zi <ziyao@...root.org> wrote:

> This controller's input and output logic is similar to previous
> generations of SoCs. Additionally, it's capable of interrupt masking,
> and could be configured to detect levels and edges, and is supplied with
> a distinct reset signal.
>
> The interrupt functionality is implemented through an irqchip, whose
> operations are written with previous generation SoCs in mind and could
> be reused. Since all Loongson SoCs with similar interrupt capability
> (LS2K1500, LS2K2000) support byte-control mode, these operations are for
> byte-control mode only for simplicity.
>
> Signed-off-by: Yao Zi <ziyao@...root.org>
> Reviewed-by: Huacai Chen <chenhuacai@...ngson.cn>

Uses generic GPIO IRQCHIP which is great,
and generic_handle_domain_irq() so I think it looks
great.
Reviewed-by: Linus Walleij <linus.walleij@...aro.org>

Yours,
Linus Walleij

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