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Message-Id: <20250904002232.322218-3-vovchkir@gmail.com>
Date: Thu, 4 Sep 2025 03:22:32 +0300
From: Vladimir Yakovlev <vovchkir@...il.com>
To: Neil Armstrong <neil.armstrong@...aro.org>,
Jessica Zhang <quic_jesszhan@...cinc.com>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>,
David Airlie <airlied@...il.com>,
Simona Vetter <simona@...ll.ch>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Cong Yang <yangcong5@...qin.corp-partner.google.com>,
dri-devel@...ts.freedesktop.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: vovchkir@...il.com
Subject: [PATCH 2/2] drm/panel: himax-hx83102: add panel starry xr109ia2t
The STARRY XR109AI2T is a 10.95" 1200x2000 (WUXGA+) TFT LCD panel with
himax-hx83102 controller. Hence, we add a new compatible with panel
specific config.
Signed-off-by: Vladimir Yakovlev <vovchkir@...il.com>
---
drivers/gpu/drm/panel/panel-himax-hx83102.c | 193 ++++++++++++++++++++
1 file changed, 193 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-himax-hx83102.c b/drivers/gpu/drm/panel/panel-himax-hx83102.c
index 2aad315aec5a..a10fb9973150 100644
--- a/drivers/gpu/drm/panel/panel-himax-hx83102.c
+++ b/drivers/gpu/drm/panel/panel-himax-hx83102.c
@@ -23,6 +23,7 @@
/* Manufacturer specific DSI commands */
#define HX83102_SETPOWER 0xb1
#define HX83102_SETDISP 0xb2
+#define HX83102_SETRGBIF 0xb3
#define HX83102_SETCYC 0xb4
#define HX83102_UNKNOWN_B6 0xb6
#define HX83102_UNKNOWN_B8 0xb8
@@ -33,6 +34,7 @@
#define HX83102_UNKNOWN_BE 0xbe
#define HX83102_SETPTBA 0xbf
#define HX83102_SETSTBA 0xc0
+#define HX83102_SETDGCLUT 0xc1
#define HX83102_SETTCON 0xc7
#define HX83102_SETRAMDMY 0xc8
#define HX83102_SETPWM 0xc9
@@ -701,6 +703,172 @@ static int starry_2082109qfh040022_50e_init(struct hx83102 *ctx)
return dsi_ctx.accum_err;
}
+static int starry_himax83102_xr109_init(struct hx83102 *ctx)
+{
+ struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
+
+ msleep(60);
+
+ hx83102_enable_extended_cmds(&dsi_ctx, true);
+
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x2C, 0xB1,
+ 0xB1, 0x2D, 0xED, 0x32, 0xD7, 0x43, 0x36,
+ 0x36, 0x36, 0x36);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xD9);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x78, 0x33);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3F);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x00, 0x47,
+ 0xB0, 0xD0, 0x00, 0x12, 0x72, 0x3C, 0x9B,
+ 0x22, 0x02, 0x02, 0x00, 0x88, 0xF0);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETRGBIF, 0x11);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x6A, 0x6A,
+ 0x6A, 0x6A, 0x6A, 0x6A, 0x6A, 0x4D, 0x6A,
+ 0x4D, 0x01, 0x95);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_B6, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETVDC, 0x1B, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xCD);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x84);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3F);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BE, 0x20);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xFC, 0xC4);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSTBA, 0x32, 0x32,
+ 0x22, 0x11, 0x33, 0xA0, 0x61, 0x08, 0xF5,
+ 0x03);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDGCLUT, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xCC);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x80);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3F);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xC6);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETRAMDMY, 0x97);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3F);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPWM, 0x00, 0x1E,
+ 0x30, 0xD4, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x08, 0x13,
+ 0x07, 0x00, 0x0E, 0xA1);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02, 0x03,
+ 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xC4);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCASCADE, 0x03);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3F);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x37, 0x06,
+ 0x00, 0x02, 0x04, 0x0C, 0xFF);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x1F, 0x11,
+ 0x1F);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x06, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x6B, 0x03, 0xAA, 0xAB, 0x0E, 0x0E, 0x03,
+ 0x03, 0x98, 0x10, 0x08, 0x00, 0x08, 0x32,
+ 0x17, 0xDE, 0x07, 0xDE, 0x32, 0x17, 0xE2,
+ 0x07, 0xE2, 0x00, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18, 0x48, 0x48, 0x18,
+ 0x18, 0x18, 0x18, 0x22, 0x23, 0x1F, 0x1F,
+ 0x1E, 0x1E, 0x24, 0x25, 0x26, 0x27, 0x28,
+ 0x29, 0x2A, 0x2B, 0x00, 0x01, 0x02, 0x03,
+ 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A,
+ 0x0B, 0x20, 0x21, 0x18, 0x18, 0x18, 0x18);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x00, 0xAA,
+ 0xAA, 0xAA, 0xAA, 0x00, 0x00, 0xAA, 0xAA,
+ 0xAA, 0xAA, 0x00, 0x00, 0xAA, 0xEA, 0xAA,
+ 0xAA, 0x00, 0x00, 0xAA, 0xEA, 0xAA, 0xAA,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGMA, 0x00, 0x02,
+ 0x08, 0x0D, 0x12, 0x18, 0x2C, 0x32, 0x38,
+ 0x34, 0x4F, 0x56, 0x5E, 0x70, 0x72, 0x7E,
+ 0x89, 0x9E, 0x9F, 0x50, 0x59, 0x62, 0x68,
+ 0x00, 0x02, 0x08, 0x0D, 0x12, 0x18, 0x2C,
+ 0x32, 0x38, 0x34, 0x4F, 0x56, 0x5E, 0x70,
+ 0x72, 0x7E, 0x89, 0x9E, 0x9F, 0x50, 0x59,
+ 0x65, 0x74);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x08, 0x10,
+ 0x10, 0x1B, 0x22, 0x95, 0x01, 0x5C, 0x97,
+ 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x12,
+ 0x05, 0x02, 0x02, 0x10, 0x33, 0x02, 0x04,
+ 0x18, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x01, 0xBF,
+ 0x11);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDGCLUT, 0x00, 0x04,
+ 0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C, 0x20,
+ 0x24, 0x28, 0x2D, 0x30, 0x35, 0x39, 0x3D,
+ 0x41, 0x46, 0x4A, 0x4E, 0x56, 0x5D, 0x65,
+ 0x6E, 0x76, 0x7E, 0x86, 0x8D, 0x96, 0x9E,
+ 0xA5, 0xAD, 0xB6, 0xBE, 0xC6, 0xCF, 0xD6,
+ 0xDE, 0xE6, 0xED, 0xF5, 0xF9, 0xFA, 0xFC,
+ 0xFE, 0xFF, 0x19, 0xA6, 0xBC, 0xDF, 0xC0,
+ 0x7D, 0x97, 0x2E, 0x24, 0xB6, 0x4D, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x86);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x3C);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xC5);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x00, 0x00,
+ 0x00, 0x80, 0x80, 0x0C, 0xA1);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3F);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x00, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0xFF, 0xFF,
+ 0xFF, 0xFF);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x02, 0x00,
+ 0x3E, 0x01, 0x83, 0x0F, 0x7E, 0x10, 0xA0,
+ 0x00, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDGCLUT, 0x00, 0x04,
+ 0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C, 0x20,
+ 0x24, 0x28, 0x2C, 0x30, 0x34, 0x39, 0x3D,
+ 0x41, 0x45, 0x49, 0x4D, 0x55, 0x5C, 0x64,
+ 0x6C, 0x75, 0x7C, 0x84, 0x8C, 0x94, 0x9C,
+ 0xA4, 0xAB, 0xB4, 0xBC, 0xC4, 0xCD, 0xD4,
+ 0xDD, 0xE5, 0xEC, 0xF4, 0xF8, 0xFA, 0xFC,
+ 0xFE, 0xFF, 0x19, 0x95, 0x6B, 0x70, 0x15,
+ 0x7B, 0x3D, 0xA6, 0x28, 0xC2, 0x94, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xCC);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x02, 0x1D,
+ 0xE0, 0x11, 0x70);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3F);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xAB, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xA0, 0xAB, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xA0);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xFB, 0x01,
+ 0xFB, 0x01, 0xFB, 0x01, 0x00, 0x00, 0x00,
+ 0x26, 0x00, 0x26, 0x81, 0x02, 0x40, 0x00,
+ 0x20, 0x94, 0x05, 0x04, 0x03, 0x02, 0x01,
+ 0x00, 0x00, 0x00, 0x01, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xC6);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x03, 0xFF,
+ 0xF0);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3F);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDGCLUT, 0x00, 0x04,
+ 0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C, 0x1F,
+ 0x24, 0x28, 0x2B, 0x2F, 0x33, 0x38, 0x3C,
+ 0x3F, 0x43, 0x47, 0x4B, 0x53, 0x5B, 0x62,
+ 0x6A, 0x73, 0x7B, 0x82, 0x8A, 0x92, 0x9A,
+ 0xA2, 0xA9, 0xB2, 0xBA, 0xC3, 0xCB, 0xD3,
+ 0xDB, 0xE4, 0xEB, 0xF3, 0xF8, 0xFA, 0xFC,
+ 0xFE, 0xFF, 0x11, 0x90, 0xC3, 0xA0, 0xFF,
+ 0xDB, 0x0D, 0x7B, 0x72, 0xA2, 0xC0, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xAA, 0xBB,
+ 0xEA, 0xAA, 0xAA, 0xA0, 0xAA, 0xBB, 0xEA,
+ 0xAA, 0xAA, 0xA0, 0xAB, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xA0, 0xAB, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xA0, 0xAA, 0xBA, 0xAA, 0xAA, 0xAA, 0xA0,
+ 0xAA, 0xBA, 0xAA, 0xAA, 0xAA, 0xA0);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xC4);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x96);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3F);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xC5);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x4F);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3F);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);
+
+ hx83102_enable_extended_cmds(&dsi_ctx, false);
+
+ mipi_dsi_msleep(&dsi_ctx, 60);
+
+ return dsi_ctx.accum_err;
+}
+
static const struct drm_display_mode starry_mode = {
.clock = 162680,
.hdisplay = 1200,
@@ -833,6 +1001,28 @@ static const struct hx83102_panel_desc starry_2082109qfh040022_50e_desc = {
.init = starry_2082109qfh040022_50e_init,
};
+static const struct drm_display_mode starry_himax83102_xr109_default_mode = {
+ .clock = 168500,
+ .hdisplay = 1200,
+ .hsync_start = 1200 + 55,
+ .hsync_end = 1200 + 55 + 20,
+ .htotal = 1200 + 55 + 20 + 40,
+ .vdisplay = 2000,
+ .vsync_start = 2000 + 116,
+ .vsync_end = 2000 + 116 + 8,
+ .vtotal = 2000 + 116 + 8 + 12,
+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+};
+
+static const struct hx83102_panel_desc starry_himax83102_xr109_desc = {
+ .modes = &starry_himax83102_xr109_default_mode,
+ .size = {
+ .width_mm = 143,
+ .height_mm = 239,
+ },
+ .init = starry_himax83102_xr109_init,
+};
+
static int hx83102_enable(struct drm_panel *panel)
{
msleep(130);
@@ -1069,6 +1259,9 @@ static const struct of_device_id hx83102_of_match[] = {
{ .compatible = "starry,himax83102-j02",
.data = &starry_desc
},
+ { .compatible = "starry,himax83102-xr109",
+ .data = &starry_himax83102_xr109_desc
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, hx83102_of_match);
--
2.34.1
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