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Message-ID: <20250904-groovy-sheep-of-wizardry-ad0ae9@kuoka>
Date: Thu, 4 Sep 2025 10:11:51 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Aaron Kling <webgeek1234@...il.com>
Cc: Rob Herring <robh@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Thierry Reding <thierry.reding@...il.com>, Jonathan Hunter <jonathanh@...dia.com>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, MyungJoo Ham <myungjoo.ham@...sung.com>, 
	Kyungmin Park <kyungmin.park@...sung.com>, Chanwoo Choi <cw00.choi@...sung.com>, 
	Dmitry Osipenko <digetx@...il.com>, linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-tegra@...r.kernel.org, linux-pm@...r.kernel.org
Subject: Re: [PATCH v2 3/8] dt-bindings: memory: tegra210: emc: Document OPP
 table and interconnect

On Wed, Sep 03, 2025 at 02:50:09PM -0500, Aaron Kling wrote:
> These are needed for dynamic frequency scaling of the EMC controller.
> 
> Signed-off-by: Aaron Kling <webgeek1234@...il.com>
> ---
>  .../bindings/memory-controllers/nvidia,tegra210-emc.yaml    | 13 +++++++++++++
>  1 file changed, 13 insertions(+)

I asked to order patches within patchset in some logical way. First
patch was memory, second other, third again memory.

There are no dependencies explained, so this looks like groupping
unrelated patches, therefore SPLIT finally the patchset per subsystem.

> 
> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
> index bc8477e7ab193b7880bb681037985f3fccebf02f..6cc1c7fc7a328bd18c7c0beb535c1ff918bcdb2a 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
> @@ -33,6 +33,9 @@ properties:
>      items:
>        - description: EMC general interrupt
>  
> +  "#interconnect-cells":
> +    const: 0
> +
>    memory-region:
>      maxItems: 1
>      description:
> @@ -44,12 +47,19 @@ properties:
>      description:
>        phandle of the memory controller node
>  
> +  operating-points-v2:
> +    description:
> +      Should contain freqs and voltages and opp-supported-hw property, which
> +      is a bitfield indicating SoC speedo ID mask.
> +

No opp-table?

>  required:
>    - compatible
>    - reg
>    - clocks
>    - clock-names
> +  - "#interconnect-cells"

That's ABI break without explanation.

>    - nvidia,memory-controller
> +  - operating-points-v2

Best regards,
Krzysztof


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