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Message-ID: <a304ec1c-7364-4926-8763-8c731e461eb9@kernel.org>
Date: Thu, 4 Sep 2025 12:52:32 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
 Sarthak Garg <quic_sartgarg@...cinc.com>,
 Ulf Hansson <ulf.hansson@...aro.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Bjorn Andersson <andersson@...nel.org>,
 Konrad Dybcio <konradybcio@...nel.org>,
 Adrian Hunter <adrian.hunter@...el.com>
Cc: linux-mmc@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
 quic_nguyenb@...cinc.com, quic_rampraka@...cinc.com,
 quic_pragalla@...cinc.com, quic_sayalil@...cinc.com,
 quic_nitirawa@...cinc.com, quic_bhaskarv@...cinc.com, kernel@....qualcomm.com
Subject: Re: [PATCH V5 4/4] arm64: dts: qcom: sm8550: Add max-sd-hs-hz
 property

On 04/09/2025 12:51, Krzysztof Kozlowski wrote:
> On 04/09/2025 10:36, Konrad Dybcio wrote:
>> On 9/3/25 10:21 AM, 'Krzysztof Kozlowski' via kernel wrote:
>>> On 03/09/2025 10:04, Sarthak Garg wrote:
>>>> Due to board-specific hardware constraints particularly related
>>>> to level shifter in this case the maximum frequency for SD High-Speed
>>>> (HS) mode must be limited to 37.5 MHz to ensure reliable operation of SD
>>>> card in HS mode.
>>>>
>>>> This is achieved by introducing the `max-sd-hs-hz` property in the
>>>> device tree, allowing the controller to operate within safe frequency
>>>> limits for HS mode.
>>>>
>>>
>>> Probably we will now replicate the same discussion... And it will be
>>> happening every time you send the same and not reflect it in commit msg.

Just to emphasize this - it will happen EVERY time.

>>>
>>> Bindings say board setup, this commit msg says board config, but the
>>> patch says SoC. This is not correct.
>>
>> Both are correct, looking at the problem from two perspectives.
>>
>> The bindings description mentions board-specific limitations (e.g. because
>> "the board's electrical design does not allow one to achieve the full rated
>> frequency that the SoC can otherwise do, in a stable way")
>>
>> Here the author tries to argue that almost all SM8550 boards are broken
>> in this sense, because the reference design did not feature the required
>> passive components, making most (derivative) designs sort of "broken by
>> default" - and only some (if any?) vendors decided to go with the
>> additional components required to lift this limitation.
>>
>> This in turn makes it fair to assume the developer experience would benefit
>> from having the SD card high speed modes always work (with the slight speed
>> cap which may not be required for the 1 or 2 designs that took the extra
>> step) without each board DT creator having to track down this property
>> separately.
> 
> And then if you send same v3, I will ask the same. Can the author

v3 -> v6

> finally write commit msgs reflecting discussions and previous disagreements?

Best regards,
Krzysztof

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