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Message-Id: <20250905025632.222422-8-cn.liweihao@gmail.com>
Date: Fri, 5 Sep 2025 10:56:31 +0800
From: WeiHao Li <cn.liweihao@...il.com>
To: heiko@...ech.de,
robh@...nel.org
Cc: hjc@...k-chips.com,
andy.yan@...k-chips.com,
krzk+dt@...nel.org,
conor+dt@...nel.org,
devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org,
linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org,
WeiHao Li <cn.liweihao@...il.com>
Subject: [PATCH v2 7/8] arm64: dts: rockchip: Add DSI for RK3368
Add the Designware MIPI DSI controller and it's port nodes.
Signed-off-by: WeiHao Li <cn.liweihao@...il.com>
---
arch/arm64/boot/dts/rockchip/rk3368.dtsi | 40 ++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 60e982a3d..1b2178726 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -869,6 +869,11 @@ vop: vop@...30000 {
vop_out: port {
#address-cells = <1>;
#size-cells = <0>;
+
+ vop_out_dsi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dsi_in_vop>;
+ };
};
};
@@ -883,6 +888,41 @@ vop_mmu: iommu@...30300 {
status = "disabled";
};
+ mipi_dsi: dsi@...60000 {
+ compatible = "rockchip,rk3368-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0x0 0xff960000 0x0 0x4000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_MIPI_DSI0>;
+ clock-names = "pclk";
+ phys = <&dphy>;
+ phy-names = "dphy";
+ resets = <&cru SRST_MIPIDSI0>;
+ reset-names = "apb";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_in: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsi_in_vop: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vop_out_dsi>;
+ };
+ };
+
+ mipi_out: port@1 {
+ reg = <1>;
+ };
+
+ };
+ };
+
dphy: phy@...68000 {
compatible = "rockchip,rk3368-dsi-dphy";
reg = <0x0 0xff968000 0x0 0x4000>;
--
2.39.5
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