linux-kernel - [PATCH v2 9/9] arm64: dts: st: Add I/O sync to eth2 pinctrl in stm32mp25-pinctrl.dtsi

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Message-ID: <20250905135547.934729-10-antonio.borneo@foss.st.com>
Date: Fri, 5 Sep 2025 15:55:47 +0200
From: Antonio Borneo <antonio.borneo@...s.st.com>
To: Linus Walleij <linus.walleij@...aro.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Maxime Coquelin <mcoquelin.stm32@...il.com>,
        Alexandre Torgue
	<alexandre.torgue@...s.st.com>,
        Bartosz Golaszewski <brgl@...ev.pl>, <linux-gpio@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-stm32@...md-mailman.stormreply.com>,
        <linux-arm-kernel@...ts.infradead.org>
CC: Antonio Borneo <antonio.borneo@...s.st.com>,
        Christophe Roullier
	<christophe.roullier@...s.st.com>,
        Fabien Dessenne
	<fabien.dessenne@...s.st.com>,
        Valentin Caron <valentin.caron@...s.st.com>
Subject: [PATCH v2 9/9] arm64: dts: st: Add I/O sync to eth2 pinctrl in stm32mp25-pinctrl.dtsi

On board stm32mp257f-ev1, the propagation delay between eth2 and
the external PHY requires a compensation to guarantee that no
packet get lost in all the working conditions.

Add I/O synchronization properties in pinctrl on all the RGMII
data pins, activating re-sampling on both edges of the clock.

Co-developed-by: Christophe Roullier <christophe.roullier@...s.st.com>
Signed-off-by: Christophe Roullier <christophe.roullier@...s.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@...s.st.com>
---
 arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
index 5ac9e72478ddd..4b4347241e30a 100644
--- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
@@ -16,6 +16,7 @@ pins1 {
 			bias-disable;
 			drive-push-pull;
 			slew-rate = <3>;
+			st,io-sync = <4>;
 		};
 		pins2 {
 			pinmux = <STM32_PINMUX('F', 8, AF10)>, /* ETH_RGMII_CLK125 */
@@ -38,6 +39,7 @@ pins4 {
 				 <STM32_PINMUX('C', 11, AF10)>, /* ETH_RGMII_RXD3 */
 				 <STM32_PINMUX('C', 3, AF10)>; /* ETH_RGMII_RX_CTL */
 			bias-disable;
+			st,io-sync = <4>;
 		};
 		pins5 {
 			pinmux = <STM32_PINMUX('F', 6, AF10)>; /* ETH_RGMII_RX_CLK */
-- 
2.34.1