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Message-ID: <20250905135547.934729-5-antonio.borneo@foss.st.com>
Date: Fri, 5 Sep 2025 15:55:42 +0200
From: Antonio Borneo <antonio.borneo@...s.st.com>
To: Linus Walleij <linus.walleij@...aro.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Alexandre Torgue
<alexandre.torgue@...s.st.com>,
Bartosz Golaszewski <brgl@...ev.pl>, <linux-gpio@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>
CC: Antonio Borneo <antonio.borneo@...s.st.com>,
Christophe Roullier
<christophe.roullier@...s.st.com>,
Fabien Dessenne
<fabien.dessenne@...s.st.com>,
Valentin Caron <valentin.caron@...s.st.com>
Subject: [PATCH v2 4/9] pinctrl: stm32: Simplify handling of backup pin status
Use C bit-field to keep the backup of the pin status, instead of
explicitly handling the bit-field through shift and mask of a u32
container.
Signed-off-by: Antonio Borneo <antonio.borneo@...s.st.com>
---
drivers/pinctrl/stm32/pinctrl-stm32.c | 70 +++++++++------------------
1 file changed, 24 insertions(+), 46 deletions(-)
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
index baf160a71c11c..741f503b6c44c 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -54,18 +54,6 @@
#define STM32_GPIO_CIDCFGR(x) (0x50 + (0x8 * (x)))
#define STM32_GPIO_SEMCR(x) (0x54 + (0x8 * (x)))
-/* custom bitfield to backup pin status */
-#define STM32_GPIO_BKP_MODE_SHIFT 0
-#define STM32_GPIO_BKP_MODE_MASK GENMASK(1, 0)
-#define STM32_GPIO_BKP_ALT_SHIFT 2
-#define STM32_GPIO_BKP_ALT_MASK GENMASK(5, 2)
-#define STM32_GPIO_BKP_SPEED_SHIFT 6
-#define STM32_GPIO_BKP_SPEED_MASK GENMASK(7, 6)
-#define STM32_GPIO_BKP_PUPD_SHIFT 8
-#define STM32_GPIO_BKP_PUPD_MASK GENMASK(9, 8)
-#define STM32_GPIO_BKP_TYPE 10
-#define STM32_GPIO_BKP_VAL 11
-
#define STM32_GPIO_CIDCFGR_CFEN BIT(0)
#define STM32_GPIO_CIDCFGR_SEMEN BIT(1)
#define STM32_GPIO_CIDCFGR_SCID_MASK GENMASK(5, 4)
@@ -100,6 +88,15 @@ struct stm32_pinctrl_group {
unsigned pin;
};
+struct stm32_pin_backup {
+ unsigned int alt:4;
+ unsigned int mode:2;
+ unsigned int bias:2;
+ unsigned int speed:2;
+ unsigned int drive:1;
+ unsigned int value:1;
+};
+
struct stm32_gpio_bank {
void __iomem *base;
struct reset_control *rstc;
@@ -110,7 +107,7 @@ struct stm32_gpio_bank {
struct irq_domain *domain;
u32 bank_nr;
u32 bank_ioport_nr;
- u32 pin_backup[STM32_GPIO_PINS_PER_BANK];
+ struct stm32_pin_backup pin_backup[STM32_GPIO_PINS_PER_BANK];
u8 irq_type[STM32_GPIO_PINS_PER_BANK];
bool secure_control;
bool rif_control;
@@ -176,38 +173,32 @@ static inline u32 stm32_gpio_get_alt(u32 function)
static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,
u32 offset, u32 value)
{
- bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);
- bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL;
+ bank->pin_backup[offset].value = value;
}
static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,
u32 mode, u32 alt)
{
- bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK |
- STM32_GPIO_BKP_ALT_MASK);
- bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT;
- bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT;
+ bank->pin_backup[offset].mode = mode;
+ bank->pin_backup[offset].alt = alt;
}
static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,
u32 drive)
{
- bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);
- bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE;
+ bank->pin_backup[offset].drive = drive;
}
static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,
u32 speed)
{
- bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;
- bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT;
+ bank->pin_backup[offset].speed = speed;
}
static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,
u32 bias)
{
- bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;
- bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;
+ bank->pin_backup[offset].bias = bias;
}
/* RIF functions */
@@ -1798,7 +1789,7 @@ static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
struct stm32_pinctrl *pctl, u32 pin)
{
const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin);
- u32 val, alt, mode, offset = stm32_gpio_pin(pin);
+ u32 mode, offset = stm32_gpio_pin(pin);
struct pinctrl_gpio_range *range;
struct stm32_gpio_bank *bank;
bool pin_is_irq;
@@ -1818,36 +1809,23 @@ static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
bank = gpiochip_get_data(range->gc);
- alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;
- alt >>= STM32_GPIO_BKP_ALT_SHIFT;
- mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;
- mode >>= STM32_GPIO_BKP_MODE_SHIFT;
-
- ret = stm32_pmx_set_mode(bank, offset, mode, alt);
+ mode = bank->pin_backup[offset].mode;
+ ret = stm32_pmx_set_mode(bank, offset, mode, bank->pin_backup[offset].alt);
if (ret)
return ret;
- if (mode == 1) {
- val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);
- val = val >> STM32_GPIO_BKP_VAL;
- __stm32_gpio_set(bank, offset, val);
- }
+ if (mode == 1)
+ __stm32_gpio_set(bank, offset, bank->pin_backup[offset].value);
- val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);
- val >>= STM32_GPIO_BKP_TYPE;
- ret = stm32_pconf_set_driving(bank, offset, val);
+ ret = stm32_pconf_set_driving(bank, offset, bank->pin_backup[offset].drive);
if (ret)
return ret;
- val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;
- val >>= STM32_GPIO_BKP_SPEED_SHIFT;
- ret = stm32_pconf_set_speed(bank, offset, val);
+ ret = stm32_pconf_set_speed(bank, offset, bank->pin_backup[offset].speed);
if (ret)
return ret;
- val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;
- val >>= STM32_GPIO_BKP_PUPD_SHIFT;
- ret = stm32_pconf_set_bias(bank, offset, val);
+ ret = stm32_pconf_set_bias(bank, offset, bank->pin_backup[offset].bias);
if (ret)
return ret;
--
2.34.1
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