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Message-Id: <20250905-b4-k230-clk-v8-3-96caa02d5428@zohomail.com>
Date: Fri, 05 Sep 2025 11:10:24 +0800
From: Xukai Wang <kingxukai@...omail.com>
To: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Xukai Wang <kingxukai@...omail.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
Conor Dooley <conor@...nel.org>
Cc: linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
Samuel Holland <samuel.holland@...ive.com>,
Troy Mitchell <TroyMitchell988@...il.com>
Subject: [PATCH v8 3/3] riscv: dts: canaan: Add clock definition for K230
This patch describes the clock controller integrated in K230 SoC
and replace dummy clocks with the real ones for UARTs.
For k230-canmv and k230-evb, they provide an additional external
pulse input through a pin to serve as clock source.
Co-developed-by: Troy Mitchell <TroyMitchell988@...il.com>
Signed-off-by: Troy Mitchell <TroyMitchell988@...il.com>
Signed-off-by: Xukai Wang <kingxukai@...omail.com>
---
arch/riscv/boot/dts/canaan/k230-canmv.dts | 11 +++++++++++
arch/riscv/boot/dts/canaan/k230-evb.dts | 11 +++++++++++
arch/riscv/boot/dts/canaan/k230.dtsi | 26 ++++++++++++++++++--------
3 files changed, 40 insertions(+), 8 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/k230-canmv.dts b/arch/riscv/boot/dts/canaan/k230-canmv.dts
index 9565915cead6ad2381ea8249b616e79575feb896..cf33a5df9ff520a0dbb408864e615f61a115b673 100644
--- a/arch/riscv/boot/dts/canaan/k230-canmv.dts
+++ b/arch/riscv/boot/dts/canaan/k230-canmv.dts
@@ -17,8 +17,19 @@ ddr: memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x20000000>;
};
+
+ timerx_pulse_in: clock-50m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
};
&uart0 {
status = "okay";
};
+
+&sysclk {
+ clocks = <&osc24m>, <&timerx_pulse_in>;
+ clock-names = "osc24m", "timer-pulse-in";
+};
diff --git a/arch/riscv/boot/dts/canaan/k230-evb.dts b/arch/riscv/boot/dts/canaan/k230-evb.dts
index f898b8e62368c3740d6795fd1e3cb0b261a460ac..24dba44955690e01e53f11d6720e60a81a9f435d 100644
--- a/arch/riscv/boot/dts/canaan/k230-evb.dts
+++ b/arch/riscv/boot/dts/canaan/k230-evb.dts
@@ -17,8 +17,19 @@ ddr: memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x20000000>;
};
+
+ timerx_pulse_in: clock-50m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
};
&uart0 {
status = "okay";
};
+
+&sysclk {
+ clocks = <&osc24m>, <&timerx_pulse_in>;
+ clock-names = "osc24m", "timer-pulse-in";
+};
diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi b/arch/riscv/boot/dts/canaan/k230.dtsi
index 95c1a3d8fb1192e30113d96d3e96329545bc6ae7..7868cd4c6c9e9d82c9271f8585a71b67738d1ca7 100644
--- a/arch/riscv/boot/dts/canaan/k230.dtsi
+++ b/arch/riscv/boot/dts/canaan/k230.dtsi
@@ -3,6 +3,7 @@
* Copyright (C) 2024 Yangyu Chen <cyy@...self.name>
*/
+#include <dt-bindings/clock/canaan,k230-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
/dts-v1/;
@@ -58,11 +59,11 @@ l2_cache: l2-cache {
};
};
- apb_clk: apb-clk-clock {
+ osc24m: clock-24m {
compatible = "fixed-clock";
- clock-frequency = <50000000>;
- clock-output-names = "apb_clk";
#clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24m";
};
soc {
@@ -89,10 +90,19 @@ clint: timer@...000000 {
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
};
+ sysclk: clock-controller@...02000 {
+ compatible = "canaan,k230-clk";
+ reg = <0x0 0x91102000 0x0 0x40>,
+ <0x0 0x91100000 0x0 0x108>;
+ clocks = <&osc24m>;
+ clock-names = "osc24m";
+ #clock-cells = <1>;
+ };
+
uart0: serial@...00000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x91400000 0x0 0x1000>;
- clocks = <&apb_clk>;
+ clocks = <&sysclk K230_LS_UART0_RATE>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -102,7 +112,7 @@ uart0: serial@...00000 {
uart1: serial@...01000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x91401000 0x0 0x1000>;
- clocks = <&apb_clk>;
+ clocks = <&sysclk K230_LS_UART1_RATE>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -112,7 +122,7 @@ uart1: serial@...01000 {
uart2: serial@...02000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x91402000 0x0 0x1000>;
- clocks = <&apb_clk>;
+ clocks = <&sysclk K230_LS_UART2_RATE>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -122,7 +132,7 @@ uart2: serial@...02000 {
uart3: serial@...03000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x91403000 0x0 0x1000>;
- clocks = <&apb_clk>;
+ clocks = <&sysclk K230_LS_UART3_RATE>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -132,7 +142,7 @@ uart3: serial@...03000 {
uart4: serial@...04000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x91404000 0x0 0x1000>;
- clocks = <&apb_clk>;
+ clocks = <&sysclk K230_LS_UART4_RATE>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
--
2.34.1
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