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Message-ID: <20250905161236.51b6ecee@donnerap>
Date: Fri, 5 Sep 2025 16:12:36 +0100
From: Andre Przywara <andre.przywara@....com>
To: Chen-Yu Tsai <wens@...nel.org>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Stephen Boyd <sboyd@...nel.org>,
Chen-Yu Tsai <wens@...e.org>, Jernej Skrabec <jernej@...nel.org>, Samuel
Holland <samuel@...lland.org>, linux-sunxi@...ts.linux.dev,
linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 3/8] clk: sunxi-ng: mp: Fix dual-divider clock rate
readback
On Sun, 31 Aug 2025 01:08:56 +0800
Chen-Yu Tsai <wens@...nel.org> wrote:
> From: Chen-Yu Tsai <wens@...e.org>
>
> When dual-divider clock support was introduced, the P divider offset was
> left out of the .recalc_rate readback function. This causes the clock
> rate to become bogus or even zero (possibly due to the P divider being
> 1, leading to a divide-by-zero).
Ah, a nice catch, thanks for that! Just curious, how did you find this?
The MMC clocks use the dual divider type as well, but I didn't observe
them being wrong?
Regardless:
> Fix this by incorporating the P divider offset into the calculation.
>
> Fixes: 45717804b75e ("clk: sunxi-ng: mp: introduce dual-divider clock")
> Signed-off-by: Chen-Yu Tsai <wens@...e.org>
Reviewed-by: Andre Przywara <andre.przywara@....com>
Thanks,
Andre
> ---
> drivers/clk/sunxi-ng/ccu_mp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu_mp.c b/drivers/clk/sunxi-ng/ccu_mp.c
> index 354c981943b6..4221b1888b38 100644
> --- a/drivers/clk/sunxi-ng/ccu_mp.c
> +++ b/drivers/clk/sunxi-ng/ccu_mp.c
> @@ -185,7 +185,7 @@ static unsigned long ccu_mp_recalc_rate(struct clk_hw *hw,
> p &= (1 << cmp->p.width) - 1;
>
> if (cmp->common.features & CCU_FEATURE_DUAL_DIV)
> - rate = (parent_rate / p) / m;
> + rate = (parent_rate / (p + cmp->p.offset)) / m;
> else
> rate = (parent_rate >> p) / m;
>
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