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Message-ID: <CAH+2xPBhD0=bv6ZJw-MjECJ9nGkwmuonxjCsx+qgXv+pdk13rw@mail.gmail.com>
Date: Fri, 5 Sep 2025 17:58:13 +0200
From: Bruno Thomsen <bruno.thomsen@...il.com>
To: Josua Mayer <josua@...id-run.com>
Cc: Alexandre Belloni <alexandre.belloni@...tlin.com>, linux-rtc@...r.kernel.org, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH] rtc: pcf2127: clear minute/second interrupt

Den man. 25. aug. 2025 kl. 19.54 skrev Josua Mayer <josua@...id-run.com>:
>
> PCF2127 can generate interrupt every full second or minute configured
> from control and status register 1, bits MI (1) and SI (0).
>
> On interrupt control register 2 bit MSF (7) is set and must be cleared
> to continue normal operation.
>
> While the driver never enables this interrupt on its own, users or
> firmware may do so - e.g. as an easy way to test the interrupt.
>
> Add preprocessor definition for MSF bit and include it in the irq
> bitmask to ensure minute and second interrupts are cleared when fired.
>
> This fixes an issue where the rtc enters a test mode and becomes
> unresponsive after a second interrupt has fired and is not cleared in
> time. In this state register writes to control registers have no
> effect and the interrupt line is kept asserted [1]:
>
> [1] userspace commands to put rtc into unresponsive state:
> $ i2cget -f -y 2 0x51 0x00
> 0x04
> $ i2cset -f -y 2 0x51 0x00 0x05 # set bit 0 SI
> $ i2cget -f -y 2 0x51 0x00
> 0x84 # bit 8 EXT_TEST set
> $ i2cset -f -y 2 0x51 0x00 0x05 # try overwrite control register
> $ i2cget -f -y 2 0x51 0x00
> 0x84 # no change
>
> Signed-off-by: Josua Mayer <josua@...id-run.com>

Reviewed-by: Bruno Thomsen <bruno.thomsen@...il.com>

> ---
>  drivers/rtc/rtc-pcf2127.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c
> index 2e1ac0c42e9323dbc6793840a265e8a663e52568..3ba1de30e89c22ae07ea319d530b58adc25b520d 100644
> --- a/drivers/rtc/rtc-pcf2127.c
> +++ b/drivers/rtc/rtc-pcf2127.c
> @@ -42,6 +42,7 @@
>  #define PCF2127_BIT_CTRL2_AF                   BIT(4)
>  #define PCF2127_BIT_CTRL2_TSF2                 BIT(5)
>  #define PCF2127_BIT_CTRL2_WDTF                 BIT(6)
> +#define PCF2127_BIT_CTRL2_MSF                  BIT(7)
>  /* Control register 3 */
>  #define PCF2127_REG_CTRL3              0x02
>  #define PCF2127_BIT_CTRL3_BLIE                 BIT(0)
> @@ -96,7 +97,8 @@
>  #define PCF2127_CTRL2_IRQ_MASK ( \
>                 PCF2127_BIT_CTRL2_AF | \
>                 PCF2127_BIT_CTRL2_WDTF | \
> -               PCF2127_BIT_CTRL2_TSF2)
> +               PCF2127_BIT_CTRL2_TSF2 | \
> +               PCF2127_BIT_CTRL2_MSF)
>
>  #define PCF2127_MAX_TS_SUPPORTED       4
>
>
> ---
> base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585
> change-id: 20250825-rtc-irq-4d17b55204eb
>
> Best regards,
> --
> Josua Mayer <josua@...id-run.com>
>
>

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