linux-kernel - [GIT PULL] RISC-V updates for v6.17-rc5

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Message-ID: <053b276c-b22b-f3e7-6c11-abe61b8ee36b@kernel.org>
Date: Fri, 5 Sep 2025 16:16:30 -0600 (MDT)
From: Paul Walmsley <pjw@...nel.org>
To: torvalds@...ux-foundation.org
cc: linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [GIT PULL] RISC-V updates for v6.17-rc5

Linus,

The following changes since commit 8f5ae30d69d7543eee0d70083daf4de8fe15d585:

  Linux 6.17-rc1 (2025-08-10 19:41:16 +0300)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux tags/riscv-for-linus-6.17-rc5

for you to fetch changes up to a03ee11b8f850bd008226c6d392da24163dfb56e:

  riscv: Fix sparse warning about different address spaces (2025-09-05 15:33:52 -0600)

----------------------------------------------------------------
Several RISC-V fixes for v6.17-rc5:

- An LTO fix for clang when building with CONFIG_CMODEL_MEDLOW

- A fix for ACPI CPPC CSR read/write return values

- Several fixes for incorrect access widths in thread_info.cpu reads

- A fix for an issue in __put_user_nocheck() that was causing the glibc
  tst-socket-timestamp test to fail

- A fix to initialize struct kexec_buf records in several kexec-related
  functions, which were generating UBSAN warnings

- Two fixes for sparse warnings

----------------------------------------------------------------
Alexandre Ghiti (2):
      riscv: Fix sparse warning in __get_user_error()
      riscv: Fix sparse warning about different address spaces

Anup Patel (1):
      ACPI: RISC-V: Fix FFH_CPPC_CSR error handling

Aurelien Jarno (1):
      riscv: uaccess: fix __put_user_nocheck for unaligned accesses

Breno Leitao (1):
      riscv: kexec: Initialize kexec_buf struct

Nathan Chancellor (1):
      riscv: Only allow LTO with CMODEL_MEDANY

Radim Krčmář (4):
      riscv: use lw when reading int cpu in new_vmalloc_check
      riscv, bpf: use lw when reading int cpu in BPF_MOV64_PERCPU_REG
      riscv, bpf: use lw when reading int cpu in bpf_get_smp_processor_id
      riscv: use lw when reading int cpu in asm_per_cpu

 arch/riscv/Kconfig                     | 2 +-
 arch/riscv/include/asm/asm.h           | 2 +-
 arch/riscv/include/asm/uaccess.h       | 8 ++++----
 arch/riscv/kernel/entry.S              | 2 +-
 arch/riscv/kernel/kexec_elf.c          | 4 ++--
 arch/riscv/kernel/kexec_image.c        | 2 +-
 arch/riscv/kernel/machine_kexec_file.c | 2 +-
 arch/riscv/net/bpf_jit_comp64.c        | 4 ++--
 drivers/acpi/riscv/cppc.c              | 4 ++--
 9 files changed, 15 insertions(+), 15 deletions(-)