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Message-ID: <20250905091002.28203-1-shubhrajyoti.datta@amd.com> Date: Fri, 5 Sep 2025 14:40:02 +0530 From: Shubhrajyoti Datta <shubhrajyoti.datta@....com> To: <linux-clk@...r.kernel.org>, <linux-kernel@...r.kernel.org> CC: <git@....com>, Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Michal Simek <michal.simek@....com>, Shubhrajyoti Datta <shubhrajyoti.datta@....com> Subject: [PATCH] clk: clocking-wizard: Fix output clock register offset for Versal platforms The output clock register offset used in clk_wzrd_register_output_clocks was incorrectly referencing 0x3C instead of 0x38, which caused misconfiguration of output dividers on Versal platforms. Correcting the off-by-one error ensures proper configuration of output clocks. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@....com> --- drivers/clk/xilinx/clk-xlnx-clock-wizard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c index 8abf12f88eb2..4f8ed6d1e5fd 100644 --- a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c +++ b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c @@ -1138,7 +1138,7 @@ static int clk_wzrd_register_output_clocks(struct device *dev, int nr_outputs) (dev, clkout_name, clk_name, 0, clk_wzrd->base, - (WZRD_CLK_CFG_REG(is_versal, 3) + i * 8), + (WZRD_CLK_CFG_REG(is_versal, 2) + i * 8), WZRD_CLKOUT_DIVIDE_SHIFT, WZRD_CLKOUT_DIVIDE_WIDTH, CLK_DIVIDER_ONE_BASED | -- 2.17.1
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