linux-kernel - Re: [PATCH phy 14/14] phy: lynx-28g: probe on per-SoC and per-instance compatible strings

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Message-ID: <x6vnufvcng4glrltmifczyv6lxoa5ybre6fq26n6zggjgwslax@ayukzkpl5jvt>
Date: Fri, 5 Sep 2025 13:41:12 +0300
From: Ioana Ciornei <ioana.ciornei@....com>
To: Vladimir Oltean <vladimir.oltean@....com>
Cc: linux-phy@...ts.infradead.org, Vinod Koul <vkoul@...nel.org>, 
	Kishon Vijay Abraham I <kishon@...nel.org>, linux-kernel@...r.kernel.org, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, devicetree@...r.kernel.org
Subject: Re: [PATCH phy 14/14] phy: lynx-28g: probe on per-SoC and
 per-instance compatible strings

On Thu, Sep 04, 2025 at 06:44:02PM +0300, Vladimir Oltean wrote:
> There are 3 SerDes blocks on LX2160A and 2 on LX2162A, and they differ
> in some aspects, namely in the number of lanes per SerDes and in the
> protocol converters instantiated per lane.
> 
> All of this justifies introducing compatible strings for each SerDes and
> some driver structures for figuring out the differences. The
> "fsl,lynx-28g" compatible string is kind of the "maximal configuration".
> It corresponds to SerDes 1 of LX2160A. If we were to treat all SerDes
> blocks like this one, we would access lanes which do not exist (0-3) and
> we would fail to reject lane modes which don't work.
> 
> Cc: Rob Herring <robh@...nel.org>
> Cc: Krzysztof Kozlowski <krzk+dt@...nel.org>
> Cc: Conor Dooley <conor+dt@...nel.org>
> Cc: devicetree@...r.kernel.org
> Signed-off-by: Vladimir Oltean <vladimir.oltean@....com>
> ---
>  drivers/phy/freescale/phy-fsl-lynx-28g.c | 97 +++++++++++++++++++++++-
>  1 file changed, 93 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
> index 91a3b3928ab4..991587c453df 100644
> --- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
> +++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
> @@ -479,9 +479,18 @@ struct lynx_28g_lane {
>  	enum lynx_lane_mode mode;
>  };
>  
> +struct lynx_info {
> +	int (*get_pccr)(enum lynx_lane_mode lane_mode, int lane,
> +			struct lynx_pccr *pccr);
> +	int (*get_pcvt_offset)(int lane, enum lynx_lane_mode mode);
> +	bool (*lane_supports_mode)(int lane, enum lynx_lane_mode mode);
> +	int first_lane;
> +};
> +
>  struct lynx_28g_priv {
>  	void __iomem *base;
>  	struct device *dev;
> +	const struct lynx_info *info;
>  	/* Serialize concurrent access to registers shared between lanes,
>  	 * like PCCn
>  	 */
> @@ -800,6 +809,79 @@ static int lynx_28g_get_pcvt_offset(int lane, enum lynx_lane_mode lane_mode)
>  	}
>  }
>  
> +static bool lx2160a_serdes1_lane_supports_mode(int lane,
> +					       enum lynx_lane_mode mode)
> +{
> +	return true;
> +}

The SerDes block#1 does have one limitations - 25G is supported on all
lanes except 2 and 3.

This is the only restriction that I discovered looking through the list
of supported SerDes 1 protocol combinations.

Ioana