linux-kernel - Re: [PATCH net-next v2 6/9] net: pcs: rzn1-miic: Make switch mode mask SoC-specific

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CA+V-a8vudqkkdZDyvsBeuKCgGBYCeA4ydMgN5b-+1nkWcQe_0w@mail.gmail.com>
Date: Fri, 5 Sep 2025 13:02:21 +0100
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Andrew Lunn <andrew@...n.ch>, Geert Uytterhoeven <geert+renesas@...der.be>
Cc: Clément Léger <clement.leger@...tlin.com>, 
	Andrew Lunn <andrew+netdev@...n.ch>, "David S. Miller" <davem@...emloft.net>, 
	Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, 
	Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Heiner Kallweit <hkallweit1@...il.com>, Russell King <linux@...linux.org.uk>, 
	Philipp Zabel <p.zabel@...gutronix.de>, Magnus Damm <magnus.damm@...il.com>, 
	Wolfram Sang <wsa+renesas@...g-engineering.com>, linux-renesas-soc@...r.kernel.org, 
	netdev@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH net-next v2 6/9] net: pcs: rzn1-miic: Make switch mode
 mask SoC-specific

Hi Andrew and Geert,

Thank you for the review.

On Thu, Sep 4, 2025 at 9:37 PM Andrew Lunn <andrew@...n.ch> wrote:
>
> On Thu, Sep 04, 2025 at 12:42:00PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > Move the hardcoded switch mode mask definition into the SoC-specific
> > miic_of_data structure. This allows each SoC to define its own mask
> > value rather than relying on a single fixed constant. For RZ/N1 the
> > mask remains GENMASK(4, 0).
> >
> > This is in preparation for adding support for RZ/T2H, where the
> > switch mode mask is GENMASK(2, 0).
>
> > -#define MIIC_MODCTRL_SW_MODE         GENMASK(4, 0)
>
> >       miic_reg_writel(miic, MIIC_MODCTRL,
> > -                     FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode));
> > +                     ((cfg_mode << __ffs(sw_mode_mask)) & sw_mode_mask));
>
> _ffs() should return 0 for both GENMASK(2,0) and GENMASK(4, 0). So
> this __ffs() is pointless.
>
Agreed.

> You might however want to add a comment that this assumption is being
> made.
>
I will add the below comment for this, so that once Geert's series [0]
hits in it can be easily searched and replaced.

/*
* TODO: Replace with FIELD_PREP() when compile-time
* constant restriction is lifted. Currently __ffs() returns 0 for sw_mode_mask.
*/

[0] https://lore.kernel.org/all/cover.1739540679.git.geert+renesas@glider.be

Cheers,
Prabhakar