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Message-ID: <20250905121515.192792-25-darwi@linutronix.de>
Date: Fri, 5 Sep 2025 14:15:04 +0200
From: "Ahmed S. Darwish" <darwi@...utronix.de>
To: Borislav Petkov <bp@...en8.de>,
Ingo Molnar <mingo@...hat.com>,
Dave Hansen <dave.hansen@...ux.intel.com>
Cc: Thomas Gleixner <tglx@...utronix.de>,
Andrew Cooper <andrew.cooper3@...rix.com>,
Sean Christopherson <seanjc@...gle.com>,
David Woodhouse <dwmw2@...radead.org>,
"H. Peter Anvin" <hpa@...or.com>,
Peter Zijlstra <peterz@...radead.org>,
Sohil Mehta <sohil.mehta@...el.com>,
John Ogness <john.ogness@...utronix.de>,
x86@...nel.org,
x86-cpuid@...ts.linux.dev,
LKML <linux-kernel@...r.kernel.org>,
"Ahmed S. Darwish" <darwi@...utronix.de>
Subject: [PATCH v5 24/35] x86/cpuid: Parse 'deterministic cache parameters' CPUID leaves
Add CPUID(0x4) and CPUID(0x8000001d) support to the CPUID parser.
Query CPUID(0x4) only for Intel, Centaur, and Zhaoxin as these are the
only x86 vendors where it is supported. Query CPUID(0x8000001d) only for
AMD and Hygon.
Define a single output parsing function for both CPUID leaves, as both
have the same subleaf cache enumeration logic.
Introduce the macro
__define_cpuid_read_function()
to avoid code duplication between the CPUID parser default read function,
cpuid_read_generic(), and the new CPUID(0x4)/CPUID(0x8000001d) parsing
logic.
Signed-off-by: Ahmed S. Darwish <darwi@...utronix.de>
---
arch/x86/include/asm/cpuid/types.h | 2 ++
arch/x86/kernel/cpu/cpuid_parser.c | 37 +++++++++++++++++++++++++-----
arch/x86/kernel/cpu/cpuid_parser.h | 6 ++++-
3 files changed, 38 insertions(+), 7 deletions(-)
diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpuid/types.h
index b54080066084..411a2a96e3ed 100644
--- a/arch/x86/include/asm/cpuid/types.h
+++ b/arch/x86/include/asm/cpuid/types.h
@@ -237,10 +237,12 @@ struct cpuid_leaves {
CPUID_LEAF ( 0x0, 0 );
CPUID_LEAF ( 0x1, 0 );
CPUID_LEAF ( 0x2, 0 );
+ CPUID_LEAF_N ( 0x4, 8 );
CPUID_LEAF ( 0x80000000, 0 );
CPUID_LEAF ( 0x80000002, 0 );
CPUID_LEAF ( 0x80000003, 0 );
CPUID_LEAF ( 0x80000004, 0 );
+ CPUID_LEAF_N ( 0x8000001d, 8 );
};
/*
diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid_parser.c
index f7dc5c78b06b..6d1dc56f11f2 100644
--- a/arch/x86/kernel/cpu/cpuid_parser.c
+++ b/arch/x86/kernel/cpu/cpuid_parser.c
@@ -22,17 +22,36 @@ static const struct cpuid_vendor_entry cpuid_vendor_entries[] = {
* Leaf read functions:
*/
-/*
- * Default CPUID parser read function
+/**
+ * __define_cpuid_parser_read_function() - Generate a CPUID parser leaf read function
+ * @suffix: Generated function name suffix (full name becomes: cpuid_read_@...fix())
+ * @_leaf_t: Type to cast the CPUID query output storage pointer
+ * @_leaf: Name of the CPUID query storage pointer
+ * @_break_c: Condition to break the CPUID parsing loop, which may reference @_leaf, and
+ * where @_leaf stores each iteration's CPUID query output.
*
* Satisfies the requirements stated at 'struct cpuid_parse_entry'->read().
+ * Define a CPUID parser read function according to the requirements stated at
+ * 'struct cpuid_parse_entry'->read().
*/
-static void cpuid_read_generic(const struct cpuid_parse_entry *e, struct cpuid_read_output *output)
-{
- for (int i = 0; i < e->maxcnt; i++, output->regs++, output->info->nr_entries++)
- cpuid_read_subleaf(e->leaf, e->subleaf + i, output->regs);
+#define __define_cpuid_parser_read_function(suffix, _leaf_t, _leaf, _break_c) \
+static void \
+cpuid_read_##suffix(const struct cpuid_parse_entry *e, struct cpuid_read_output *output) \
+{ \
+ struct _leaf_t *_leaf = (struct _leaf_t *)output->regs; \
+ \
+ for (int i = 0; i < e->maxcnt; i++, _leaf++, output->info->nr_entries++) { \
+ cpuid_read_subleaf(e->leaf, e->subleaf + i, _leaf); \
+ if (_break_c) \
+ break; \
+ } \
}
+/*
+ * Default CPUID parser read function
+ */
+__define_cpuid_parser_read_function(generic, cpuid_regs, ignored, false);
+
static void cpuid_read_0x2(const struct cpuid_parse_entry *e, struct cpuid_read_output *output)
{
union leaf_0x2_regs *regs = (union leaf_0x2_regs *)output->regs;
@@ -71,6 +90,12 @@ static void cpuid_read_0x2(const struct cpuid_parse_entry *e, struct cpuid_read_
output->info->nr_entries = 1;
}
+/*
+ * Shared read function for Intel CPUID(0x4) and AMD CPUID(0x8000001d), as both have
+ * the same subleaf enumeration logic and register output format.
+ */
+__define_cpuid_parser_read_function(deterministic_cache, leaf_0x4_n, l, l->cache_type == 0);
+
static void cpuid_read_0x80000000(const struct cpuid_parse_entry *e, struct cpuid_read_output *output)
{
struct leaf_0x80000000_0 *el0 = (struct leaf_0x80000000_0 *)output->regs;
diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid_parser.h
index 7366e8468116..227ffac6b297 100644
--- a/arch/x86/kernel/cpu/cpuid_parser.h
+++ b/arch/x86/kernel/cpu/cpuid_parser.h
@@ -138,12 +138,14 @@ struct cpuid_parse_entry {
* vendor entry, are treated by the CPUID parser as valid for all x86 vendors.
*/
#define CPUID_COMMON_PARSE_ENTRIES \
- /* Leaf Subleaf Reader function */ \
+ /* Leaf Static subleaf Reader function */ \
CPUID_PARSE_ENTRY ( 0x2, 0, 0x2 ), \
+ CPUID_PARSE_ENTRY_N ( 0x4, deterministic_cache ), \
CPUID_PARSE_ENTRY ( 0x80000000, 0, 0x80000000 ), \
CPUID_PARSE_ENTRY ( 0x80000002, 0, generic ), \
CPUID_PARSE_ENTRY ( 0x80000003, 0, generic ), \
CPUID_PARSE_ENTRY ( 0x80000004, 0, generic ), \
+ CPUID_PARSE_ENTRY_N ( 0x8000001d, deterministic_cache ), \
/*
* CPUID parser tables repository:
@@ -177,5 +179,7 @@ struct cpuid_vendor_entry {
#define CPUID_VENDOR_ENTRIES \
/* Leaf Vendor list */ \
CPUID_VENDOR_ENTRY(0x2, X86_VENDOR_INTEL, X86_VENDOR_CENTAUR, X86_VENDOR_ZHAOXIN),\
+ CPUID_VENDOR_ENTRY(0x4, X86_VENDOR_INTEL, X86_VENDOR_CENTAUR, X86_VENDOR_ZHAOXIN),\
+ CPUID_VENDOR_ENTRY(0x8000001d, X86_VENDOR_AMD, X86_VENDOR_HYGON), \
#endif /* _ARCH_X86_CPUID_PARSER_H */
--
2.50.1
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