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Message-ID: <20250906135345.241229-22-clamor95@gmail.com> Date: Sat, 6 Sep 2025 16:53:42 +0300 From: Svyatoslav Ryhel <clamor95@...il.com> To: Thierry Reding <thierry.reding@...il.com>, Thierry Reding <treding@...dia.com>, Mikko Perttunen <mperttunen@...dia.com>, Jonathan Hunter <jonathanh@...dia.com>, Sowjanya Komatineni <skomatineni@...dia.com>, Luca Ceresoli <luca.ceresoli@...tlin.com>, David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>, Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>, Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Prashant Gaikwad <pgaikwad@...dia.com>, Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Mauro Carvalho Chehab <mchehab@...nel.org>, Greg Kroah-Hartman <gregkh@...uxfoundation.org>, Svyatoslav Ryhel <clamor95@...il.com>, Dmitry Osipenko <digetx@...il.com>, Jonas Schwöbel <jonasschwoebel@...oo.de>, Charan Pedumuru <charan.pedumuru@...il.com> Cc: dri-devel@...ts.freedesktop.org, devicetree@...r.kernel.org, linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org, linux-media@...r.kernel.org, linux-clk@...r.kernel.org, linux-staging@...ts.linux.dev Subject: [PATCH v2 21/23] dt-bindings: display: tegra: document Tegra20 and Tegra30 CSI Document CSI HW block found in Tegra20 and Tegra30 SoC. Signed-off-by: Svyatoslav Ryhel <clamor95@...il.com> --- .../display/tegra/nvidia,tegra20-csi.yaml | 104 ++++++++++++++++ .../display/tegra/nvidia,tegra30-csi.yaml | 115 ++++++++++++++++++ 2 files changed, 219 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra30-csi.yaml diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml new file mode 100644 index 000000000000..1a2858a5893c --- /dev/null +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-csi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra20 CSI controller + +maintainers: + - Svyatoslav Ryhel <clamor95@...il.com> + +properties: + compatible: + enum: + - nvidia,tegra20-csi + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + avdd-dsi-csi-supply: + description: DSI/CSI power supply. Must supply 1.2 V. + + power-domains: + maxItems: 1 + + "#nvidia,mipi-calibrate-cells": + description: The number of cells in a MIPI calibration specifier. + Should be 1. The single cell specifies an id of the pads that + need to be calibrated for a given device. + $ref: /schemas/types.yaml#/definitions/uint32 + const: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^channel@[0-1]$": + type: object + description: channel 0 represents CSI-A and 1 represents CSI-B + additionalProperties: false + + properties: + reg: + maxItems: 1 + + nvidia,mipi-calibrate: + description: Should contain a phandle and a specifier specifying + which pads are used by this DSI output and need to be + calibrated. 0 is for CSI-A, 1 is for CSI-B, 2 is for DSI. + $ref: /schemas/types.yaml#/definitions/phandle-array + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: port receiving the video stream from the sensor + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: true + + required: + - data-lanes + + required: + - endpoint + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: port sending the video stream to the VI + + required: + - reg + - "#address-cells" + - "#size-cells" + - port@0 + - port@1 + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - power-domains + - "#address-cells" + - "#size-cells" + +# see nvidia,tegra20-vi.yaml for an example diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra30-csi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra30-csi.yaml new file mode 100644 index 000000000000..ea5ebd2f3c65 --- /dev/null +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra30-csi.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra30-csi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra30 CSI controller + +maintainers: + - Svyatoslav Ryhel <clamor95@...il.com> + +properties: + compatible: + enum: + - nvidia,tegra30-csi + + reg: + maxItems: 1 + + clocks: + items: + - description: module clock + - description: PAD A clock + - description: PAD B clock + + clock-names: + items: + - const: csi + - const: csia-pad + - const: csib-pad + + avdd-dsi-csi-supply: + description: DSI/CSI power supply. Must supply 1.2 V. + + power-domains: + maxItems: 1 + + "#nvidia,mipi-calibrate-cells": + description: The number of cells in a MIPI calibration specifier. + Should be 1. The single cell specifies an id of the pads that + need to be calibrated for a given device. + $ref: /schemas/types.yaml#/definitions/uint32 + const: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^channel@[0-1]$": + type: object + description: channel 0 represents CSI-A and 1 represents CSI-B + additionalProperties: false + + properties: + reg: + maxItems: 1 + + nvidia,mipi-calibrate: + description: Should contain a phandle and a specifier specifying + which pads are used by this DSI output and need to be + calibrated. 0 is for CSI-A, 1 is for CSI-B, 2 is for DSI-A and + 3 is for DSI-B + $ref: /schemas/types.yaml#/definitions/phandle-array + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: port receiving the video stream from the sensor + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: true + + required: + - data-lanes + + required: + - endpoint + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: port sending the video stream to the VI + + required: + - reg + - "#address-cells" + - "#size-cells" + - port@0 + - port@1 + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + - "#address-cells" + - "#size-cells" + +# see nvidia,tegra20-vi.yaml for an example -- 2.48.1
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