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Message-ID: <13801600.O9o76ZdvQC@workhorse>
Date: Sat, 06 Sep 2025 19:54:46 +0200
From: Nicolas Frattaroli <nicolas.frattaroli@...labora.com>
To: Rob Herring <robh@...nel.org>
Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
Boris Brezillon <boris.brezillon@...labora.com>,
Steven Price <steven.price@....com>, Liviu Dudau <liviu.dudau@....com>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
MyungJoo Ham <myungjoo.ham@...sung.com>,
Kyungmin Park <kyungmin.park@...sung.com>,
Chanwoo Choi <cw00.choi@...sung.com>, Jassi Brar <jassisinghbrar@...il.com>,
Kees Cook <kees@...nel.org>, "Gustavo A. R. Silva" <gustavoars@...nel.org>,
Chia-I Wu <olvaffe@...il.com>, Chen-Yu Tsai <wenst@...omium.org>,
kernel@...labora.com, dri-devel@...ts.freedesktop.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-mediatek@...ts.infradead.org,
linux-pm@...r.kernel.org, linux-hardening@...r.kernel.org
Subject:
Re: [PATCH RFC 01/10] dt-bindings: gpu: mali-valhall-csf: add
mediatek,mt8196-mali variant
Hi Rob,
On Saturday, 6 September 2025 01:26:57 Central European Summer Time Rob Herring wrote:
> On Fri, Sep 05, 2025 at 12:22:57PM +0200, Nicolas Frattaroli wrote:
> > The Mali-based GPU on the MediaTek MT8196 SoC is shackled to its concept
> > of "MFlexGraphics", which in this iteration includes an embedded MCU
> > that needs to be poked to power on the GPU, and is in charge of
> > controlling all the clocks and regulators.
> >
> > In return, it lets us omit the OPP tables from the device tree, as those
> > can now be enumerated at runtime from the MCU.
> >
> > Add the mediatek,mt8196-mali compatible, and a performance-controller
> > property which points to a node representing such setups. It's required
> > on mt8196 devices.
> >
> > Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@...labora.com>
> > ---
> > .../bindings/gpu/arm,mali-valhall-csf.yaml | 36 +++++++++++++++++++++-
> > 1 file changed, 35 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
> > index a5b4e00217587c5d1f889094e2fff7b76e6148eb..6df802e900b744d226395c29f8d87fb6d3282d26 100644
> > --- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
> > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
> > @@ -19,6 +19,7 @@ properties:
> > - items:
> > - enum:
> > - rockchip,rk3588-mali
> > + - mediatek,mt8196-mali
> > - const: arm,mali-valhall-csf # Mali Valhall GPU model/revision is fully discoverable
> >
> > reg:
> > @@ -53,6 +54,13 @@ properties:
> > opp-table:
> > type: object
> >
> > + performance-controller:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description:
> > + A phandle of a device that controls this GPU's power and frequency,
> > + if any. If present, this is usually in the form of some specialised
> > + embedded MCU.
>
> We already abuse power-domains binding with both power and performance.
> There's a performance-domain binding too, but only used on one platform
> for CPUs (Mediatek too IIRC). Or perhaps you could just point to an
> empty OPP table. I don't think you have anything new here, so don't
> invent something new.
Oops, yeah, I forgot about performance-domain already existing. I agree
that it looks like a good fit; iirc I initially disregarded it because
I thought it was an actual heterogenous core cpufreq-y thing I'd be
overloading with new meaning, but I see now that this is not so, and
aside from mediatek, Apple appears to be the only user.
Thanks for the fast review.
Kind regards,
Nicolas Frattaroli
>
> Rob
>
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