linux-kernel - Re: [PATCH v3 26/32] clk: at91: at91sam9x5: switch to parent_hw and parent

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Message-ID: <41cf6626-ce6f-408f-bcbd-299866d70fe0@tuxon.dev>
Date: Sat, 6 Sep 2025 21:52:04 +0300
From: Claudiu Beznea <claudiu.beznea@...on.dev>
To: Ryan.Wanner@...rochip.com, mturquette@...libre.com, sboyd@...nel.org,
 nicolas.ferre@...rochip.com, alexandre.belloni@...tlin.com
Cc: varshini.rajendran@...rochip.com, linux-clk@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
 robh@...nel.org
Subject: Re: [PATCH v3 26/32] clk: at91: at91sam9x5: switch to parent_hw and
 parent_data



On 9/3/25 18:16, claudiu beznea wrote:
> 
> 
> On 7/10/25 23:07, Ryan.Wanner@...rochip.com wrote:
>> From: Claudiu Beznea <claudiu.beznea@...on.dev>
>>
>> Switch AT91SAM9X5 clocks to use parent_hw and parent_data. Having
>> parent_hw instead of parent names improves to clock registration
>> speed and re-parenting.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea@...on.dev>
>> Signed-off-by: Ryan Wanner <Ryan.Wanner@...rochip.com>
>> ---
>>   drivers/clk/at91/at91sam9x5.c | 125 ++++++++++++++++++----------------
>>   1 file changed, 65 insertions(+), 60 deletions(-)
>>
>> diff --git a/drivers/clk/at91/at91sam9x5.c b/drivers/clk/at91/at91sam9x5.c
>> index 13331e015dd7..f6138622ab50 100644
>> --- a/drivers/clk/at91/at91sam9x5.c
>> +++ b/drivers/clk/at91/at91sam9x5.c
>> @@ -38,9 +38,9 @@ static const struct clk_pll_characteristics
>> plla_characteristics = {
>>       .out = plla_out,
>>   };
>>   -static const struct {
>> +static struct {
>>       char *n;
>> -    char *p;
>> +    struct clk_hw *parent_hw;
>>       unsigned long flags;
>>       u8 id;
>>   } at91sam9x5_systemck[] = {
>> @@ -48,12 +48,12 @@ static const struct {
>>        * ddrck feeds DDR controller and is enabled by bootloader thus we
>> need
>>        * to keep it enabled in case there is no Linux consumer for it.
>>        */
>> -    { .n = "ddrck", .p = "masterck_div", .id = 2, .flags =
>> CLK_IS_CRITICAL },
>> -    { .n = "smdck", .p = "smdclk",   .id = 4 },
>> -    { .n = "uhpck", .p = "usbck",    .id = 6 },
>> -    { .n = "udpck", .p = "usbck",    .id = 7 },
>> -    { .n = "pck0",  .p = "prog0",    .id = 8 },
>> -    { .n = "pck1",  .p = "prog1",    .id = 9 },
>> +    { .n = "ddrck", .id = 2, .flags = CLK_IS_CRITICAL },
>> +    { .n = "smdck", .id = 4 },
>> +    { .n = "uhpck", .id = 6 },
>> +    { .n = "udpck", .id = 7 },
>> +    { .n = "pck0",  .id = 8 },
>> +    { .n = "pck1",  .id = 9 },
>>   };
>>     static const struct clk_pcr_layout at91sam9x5_pcr_layout = {
>> @@ -133,25 +133,16 @@ static void __init at91sam9x5_pmc_setup(struct
>> device_node *np,
>>                       const struct pck *extra_pcks,
>>                       bool has_lcdck)
>>   {
>> +    const char *slow_clk_name = "slowck", *main_xtal_name = "main_xtal";
>> +    struct clk_hw *main_rc_hw, *main_osc_hw, *hw;
>> +    u8 slow_clk_index = 0, main_xtal_index = 0;
>>       struct clk_range range = CLK_RANGE(0, 0);
>> -    const char *slck_name, *mainxtal_name;
>> +    struct clk_parent_data parent_data[6];
>> +    struct clk_hw *smdck_hw, *usbck_hw;
>>       struct pmc_data *at91sam9x5_pmc;
>> -    const char *parent_names[6];
>>       struct regmap *regmap;
>> -    struct clk_hw *hw;
>> -    int i;
>>       bool bypass;
>> -
>> -    i = of_property_match_string(np, "clock-names", "slow_clk");
>> -    if (i < 0)
>> -        return;
>> -
>> -    slck_name = of_clk_get_parent_name(np, i);
>> -
>> -    i = of_property_match_string(np, "clock-names", "main_xtal");
>> -    if (i < 0)
>> -        return;
>> -    mainxtal_name = of_clk_get_parent_name(np, i);

Same here, and same for the rest of conversion patches.