linux-kernel - [GIT PULL] clk: thead: Updates for v6.18

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Message-ID: <aLyHtxrU4mGFfnFs@x1>
Date: Sat, 6 Sep 2025 12:12:55 -0700
From: Drew Fustini <fustini@...nel.org>
To: Stephen Boyd <sboyd@...nel.org>
Cc: linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-riscv@...ts.infradead.org,
	Michal Wilczynski <m.wilczynski@...sung.com>,
	Yao Zi <ziyao@...root.org>, Icenowy Zheng <uwu@...nowy.me>
Subject: [GIT PULL] clk: thead: Updates for v6.18

The following changes since commit 8f5ae30d69d7543eee0d70083daf4de8fe15d585:

  Linux 6.17-rc1 (2025-08-10 19:41:16 +0300)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux.git tags/thead-clk-for-v6.18

for you to fetch changes up to c567bc5fc68c4388c00e11fc65fd14fe86b52070:

  clk: thead: th1520-ap: set all AXI clocks to CLK_IS_CRITICAL (2025-08-18 14:58:23 -0700)

----------------------------------------------------------------
T-HEAD clock changes for v6.18

Updates for the T-HEAD TH1520 clock controller:

 - Describe gate clocks with clk_gate so that clock gates can be clock
   parents. This is similar to the mux clock refactor in 54edba916e29
   ("clk: thead: th1520-ap: Describe mux clocks with clk_mux").

 - Add support for enabling/disabling PLLs. Some PLLs are put into a
   disabled state by the bootloader, and clock driver now has the
   ability to enable them.

 - Set all AXI clocks to CLK_IS_CRITICAL. The AXI crossbar of TH1520 has
   no proper timeout handling, which means gating AXI clocks can easily
   lead to bus timeout and hang the system. All these clock gates are
   ungated by default on system reset.

 - Convert all current CLK_IGNORE_UNUSED usage to CLK_IS_CRITICAL to
   prevent unwanted clock gating.

 - Fix parent of padctrl0 clock, fix parent of DPU pixel clocks and
   support changing DPU pixel clock rate.

All changes have been tested in linux-next.

Signed-off-by: Drew Fustini <fustini@...nel.org>

----------------------------------------------------------------
Icenowy Zheng (5):
      clk: thead: th1520-ap: describe gate clocks with clk_gate
      clk: thead: th1520-ap: fix parent of padctrl0 clock
      clk: thead: add support for enabling/disabling PLLs
      clk: thead: support changing DPU pixel clock rate
      clk: thead: th1520-ap: set all AXI clocks to CLK_IS_CRITICAL

Michal Wilczynski (1):
      clk: thead: Correct parent for DPU pixel clocks

 drivers/clk/thead/clk-th1520-ap.c | 503 ++++++++++++++++++++++----------------
 1 file changed, 292 insertions(+), 211 deletions(-)