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Message-ID: <20250906191717.GA1639859-robh@kernel.org>
Date: Sat, 6 Sep 2025 14:17:17 -0500
From: Rob Herring <robh@...nel.org>
To: David Yang <mmyangfl@...il.com>
Cc: netdev@...r.kernel.org, Andrew Lunn <andrew@...n.ch>,
Vladimir Oltean <olteanv@...il.com>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Simon Horman <horms@...nel.org>,
Russell King <linux@...linux.org.uk>, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Subject: Re: [PATCH net-next v7 1/3] dt-bindings: net: dsa: yt921x: Add
Motorcomm YT921x switch support
On Sat, Sep 06, 2025 at 02:17:21AM +0800, David Yang wrote:
> The Motorcomm YT921x series is a family of Ethernet switches with up to
> 8 internal GbE PHYs and up to 2 GMACs.
A couple of nits below if you spin another version.
>
> Signed-off-by: David Yang <mmyangfl@...il.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> ---
> .../bindings/net/dsa/motorcomm,yt921x.yaml | 169 ++++++++++++++++++
> 1 file changed, 169 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/dsa/motorcomm,yt921x.yaml
>
> diff --git a/Documentation/devicetree/bindings/net/dsa/motorcomm,yt921x.yaml b/Documentation/devicetree/bindings/net/dsa/motorcomm,yt921x.yaml
> new file mode 100644
> index 000000000000..275f5feb0160
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/dsa/motorcomm,yt921x.yaml
> @@ -0,0 +1,169 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/dsa/motorcomm,yt921x.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Motorcomm YT921x Ethernet switch family
> +
> +maintainers:
> + - David Yang <mmyangfl@...il.com>
> +
> +description: |
> + The Motorcomm YT921x series is a family of Ethernet switches with up to 8
> + internal GbE PHYs and up to 2 GMACs, including:
> +
> + - YT9215S / YT9215RB / YT9215SC: 5 GbE PHYs (Port 0-4) + 2 GMACs (Port 8-9)
> + - YT9213NB: 2 GbE PHYs (Port 1/3) + 1 GMAC (Port 9)
> + - YT9214NB: 2 GbE PHYs (Port 1/3) + 2 GMACs (Port 8-9)
> + - YT9218N: 8 GbE PHYs (Port 0-7)
> + - YT9218MB: 8 GbE PHYs (Port 0-7) + 2 GMACs (Port 8-9)
> +
> + Any port can be used as the CPU port.
> +
> +properties:
> + compatible:
> + const: motorcomm,yt9215
> +
> + reg:
> + enum: [0x0, 0x1d]
> +
> + reset-gpios:
> + maxItems: 1
> +
> + mdio:
> + $ref: /schemas/net/mdio.yaml#
> + unevaluatedProperties: false
> + description: |
Don't need '|'.
> + Internal MDIO bus for the internal GbE PHYs. PHYs 0-7 are used for Port
> + 0-7 respectively.
> +
> + mdio-external:
> + $ref: /schemas/net/mdio.yaml#
> + unevaluatedProperties: false
> + description: |
Don't need '|'.
> + External MDIO bus to access external components. External PHYs for GMACs
> + (Port 8-9) are expected to be connected to the external MDIO bus in
> + vendor's reference design, but that is not a hard limitation from the
> + chip.
> +
> +required:
> + - compatible
> + - reg
> +
> +allOf:
> + - $ref: dsa.yaml#/$defs/ethernet-ports
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/gpio/gpio.h>
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + switch@1d {
> + compatible = "motorcomm,yt9215";
> + /* default 0x1d, alternate 0x0 */
> + reg = <0x1d>;
> + reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + sw_phy0: phy@0 {
> + reg = <0x0>;
> + };
> +
> + sw_phy1: phy@1 {
> + reg = <0x1>;
> + };
> +
> + sw_phy2: phy@2 {
> + reg = <0x2>;
> + };
> +
> + sw_phy3: phy@3 {
> + reg = <0x3>;
> + };
> +
> + sw_phy4: phy@4 {
> + reg = <0x4>;
> + };
> + };
> +
> + mdio-external {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + phy1: phy@b {
> + reg = <0xb>;
> + };
> + };
> +
> + ports {
ethernet-ports
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
ethernet-port
> + reg = <0>;
> + label = "lan1";
> + phy-mode = "internal";
> + phy-handle = <&sw_phy0>;
> + };
> +
> + port@1 {
> + reg = <1>;
> + label = "lan2";
> + phy-mode = "internal";
> + phy-handle = <&sw_phy1>;
> + };
> +
> + port@2 {
> + reg = <2>;
> + label = "lan3";
> + phy-mode = "internal";
> + phy-handle = <&sw_phy2>;
> + };
> +
> + port@3 {
> + reg = <3>;
> + label = "lan4";
> + phy-mode = "internal";
> + phy-handle = <&sw_phy3>;
> + };
> +
> + port@4 {
> + reg = <4>;
> + label = "lan5";
> + phy-mode = "internal";
> + phy-handle = <&sw_phy4>;
> + };
> +
> + /* CPU port */
> + port@8 {
> + reg = <8>;
> + phy-mode = "sgmii";
> + ethernet = <ð0>;
> +
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + pause;
> + asym-pause;
> + };
> + };
> +
> + /* if external phy is connected to a MAC */
> + port@9 {
> + reg = <9>;
> + label = "wan";
> + phy-mode = "rgmii";
> + phy-handle = <&phy1>;
> + };
> + };
> + };
> + };
> --
> 2.50.1
>
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