linux-kernel - Re: [PATCH] drm/msm: Sync GPU registers from mesa

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Message-ID: <dnnkrq64cwkoazl3e7om22u4ein4mvn52otm2kyd6hcfuk4keu@rga7l6rbvvsq>
Date: Sun, 7 Sep 2025 01:19:23 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Rob Clark <rob.clark@....qualcomm.com>
Cc: dri-devel@...ts.freedesktop.org, freedreno@...ts.freedesktop.org,
        linux-arm-msm@...r.kernel.org,
        Karmjit Mahil <karmjit.mahil@...lia.com>, Sean Paul <sean@...rly.run>,
        Konrad Dybcio <konradybcio@...nel.org>,
        Dmitry Baryshkov <lumag@...nel.org>,
        Abhinav Kumar <abhinav.kumar@...ux.dev>,
        Jessica Zhang <jessica.zhang@....qualcomm.com>,
        Marijn Suijten <marijn.suijten@...ainline.org>,
        David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
        open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] drm/msm: Sync GPU registers from mesa

On Sat, Sep 06, 2025 at 03:05:25PM -0700, Rob Clark wrote:
> On Sat, Sep 6, 2025 at 11:55 AM Dmitry Baryshkov
> <dmitry.baryshkov@....qualcomm.com> wrote:
> >
> > On Sat, Sep 06, 2025 at 10:05:40AM -0700, Rob Clark wrote:
> > > In particular, to pull in a SP_READ_SEL_LOCATION bitfield size fix to
> > > fix a7xx GPU snapshot.
> > >
> > > Sync from mesa commit 76fece61c6ff ("freedreno/registers: Add A7XX_CX_DBGC")
> > >
> > > Cc: Karmjit Mahil <karmjit.mahil@...lia.com>
> > > Signed-off-by: Rob Clark <robin.clark@....qualcomm.com>
> > > ---
> > >  drivers/gpu/drm/msm/adreno/a6xx_catalog.c     |  10 +-
> > >  drivers/gpu/drm/msm/adreno/a6xx_gpu.c         |  19 +-
> > >  drivers/gpu/drm/msm/adreno/a6xx_preempt.c     |   5 +-
> > >  drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 718 ++++++++++--------
> > >  .../msm/registers/adreno/a6xx_descriptors.xml |  40 -
> > >  .../drm/msm/registers/adreno/a6xx_enums.xml   |  50 +-
> > >  .../drm/msm/registers/adreno/adreno_pm4.xml   | 179 ++---
> > >  7 files changed, 524 insertions(+), 497 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > index 2e2090f52e26..3f5c4bcf32cc 100644
> > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > @@ -247,8 +247,8 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
> > >        * Needed for preemption
> > >        */
> > >       OUT_PKT7(ring, CP_MEM_WRITE, 5);
> > > -     OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr)));
> > > -     OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr)));
> > > +     OUT_RING(ring, lower_32_bits(memptr));
> > > +     OUT_RING(ring, upper_32_bits(memptr));
> >
> > Could you please comment, why are we droping all these accessors?
> 
> We redefined these addresses as reg64 so there is no longer HI/LO
> regs.. which works better for the c++ builders in userspace but means
> these accessors no longer are generated.

This should probably go to the commit message.

> 
> I suppose we could perhaps make gen_header.py generate legacy hi/lo
> regs from the reg64 for the "legacy" C builders..

> 
> BR,
> -R
> 
> >
> > >       OUT_RING(ring, lower_32_bits(ttbr));
> > >       OUT_RING(ring, upper_32_bits(ttbr));
> > >       OUT_RING(ring, ctx->seqno);
> > > @@ -278,9 +278,8 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
> > >                */
> > >               OUT_PKT7(ring, CP_WAIT_REG_MEM, 6);
> > >               OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ));
> > > -             OUT_RING(ring, CP_WAIT_REG_MEM_1_POLL_ADDR_LO(
> > > -                             REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS));
> > > -             OUT_RING(ring, CP_WAIT_REG_MEM_2_POLL_ADDR_HI(0));
> > > +             OUT_RING(ring, REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS);
> > > +             OUT_RING(ring, 0);
> > >               OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(0x1));
> > >               OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(0x1));
> > >               OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0));
> > > @@ -1320,14 +1319,14 @@ static int hw_init(struct msm_gpu *gpu)
> > >
> > >       /* Set weights for bicubic filtering */
> > >       if (adreno_is_a650_family(adreno_gpu) || adreno_is_x185(adreno_gpu)) {
> > > -             gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0);
> > > -             gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
> > > +             gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(0), 0);
> > > +             gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(1),
> > >                       0x3fe05ff4);
> > > -             gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2,
> > > +             gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(2),
> > >                       0x3fa0ebee);
> > > -             gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3,
> > > +             gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(3),
> > >                       0x3f5193ed);
> > > -             gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4,
> > > +             gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(4),
> > >                       0x3f0243f0);
> > >       }
> > >
> >
> > --
> > With best wishes
> > Dmitry

-- 
With best wishes
Dmitry