linux-kernel - RE: [PATCH v2 2/2] pinctrl: renesas: rzg2l: Drop the unnecessary pin configurations

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Message-ID:
 <TY3PR01MB11346A6C80A312D3A0E91331C860CA@TY3PR01MB11346.jpnprd01.prod.outlook.com>
Date: Mon, 8 Sep 2025 14:20:38 +0000
From: Biju Das <biju.das.jz@...renesas.com>
To: geert <geert@...ux-m68k.org>, biju.das.au <biju.das.au@...il.com>
CC: Linus Walleij <linus.walleij@...aro.org>, Prabhakar Mahadev Lad
	<prabhakar.mahadev-lad.rj@...renesas.com>,
	"linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>,
	"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v2 2/2] pinctrl: renesas: rzg2l: Drop the unnecessary pin
 configurations

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@...ux-m68k.org>
> Sent: 05 September 2025 11:00
> Subject: Re: [PATCH v2 2/2] pinctrl: renesas: rzg2l: Drop the unnecessary pin configurations
> 
> Hi Biju,
> 
> On Sun, 17 Aug 2025 at 16:30, Biju <biju.das.au@...il.com> wrote:
> > From: Biju Das <biju.das.jz@...renesas.com>
> >
> > There is no need to reconfigure the pin if the pin's configuration
> > values are same as the reset values. E.g.: PS0 pin configuration for
> > NMI function is PMC = 1 and PFC = 0 and is same as that of reset
> > values. Currently the code is first setting it to GPIO HI-Z state and
> > then again reconfiguring to NMI function leading to spurious IRQ. Drop
> > the unnecessary pin configurations from the driver.
> >
> > Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
> 
> Thanks for your patch!
> 
> > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > @@ -539,7 +539,11 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
> >                                        u8 pin, u8 off, u8 func)  {
> >         unsigned long flags;
> > -       u32 reg;
> > +       u32 reg, pfc;
> > +
> > +       pfc = readl(pctrl->base + PFC(off));
> 
> As the read value may be used later, shouldn't it be read while holding the spinlock below?

OK will hold spinlock above.

> 
> > +       if (((pfc >> (pin * 4)) & PFC_MASK)  == func)
> 
> Please drop the second space before the == operator.

Will drop.

> 
> > +               return;
> 
> What if the pin is currently configured for GPIO in the PMC register?
> According to the documentation, that is even the initial state after reset.

Ok will update the logic, Do not switch if the reset values is same
as pin function value. 

       /* Switching to GPIO is not required if reset value is same as func */   
        reg = readb(pctrl->base + PMC(off));                                     
        spin_lock_irqsave(&pctrl->lock, flags);                                  
        pfc = readl(pctrl->base + PFC(off));                                     
        if ((reg & BIT(pin)) && (((pfc >> (pin * 4)) & PFC_MASK) == func)) {     
		spin_unlock_irqrestore(&pctrl->lock, flags);                     
		return;  
	  }                                                        

> 
> >
> >         spin_lock_irqsave(&pctrl->lock, flags);
> >
> > @@ -555,9 +559,8 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
> >         writeb(reg & ~BIT(pin), pctrl->base + PMC(off));
> >
> >         /* Select Pin function mode with PFC register */
> > -       reg = readl(pctrl->base + PFC(off));
> > -       reg &= ~(PFC_MASK << (pin * 4));
> > -       writel(reg | (func << (pin * 4)), pctrl->base + PFC(off));
> > +       pfc &= ~(PFC_MASK << (pin * 4));
> > +       writel(pfc | (func << (pin * 4)), pctrl->base + PFC(off));
> >
> >         /* Switch to Peripheral pin function with PMC register */
> >         reg = readb(pctrl->base + PMC(off)); @@ -3103,11 +3106,18 @@
> > static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)
> >                 pm = readw(pctrl->base + PM(off));
> >                 for_each_set_bit(pin, &pinmap, max_pin) {
> >                         struct rzg2l_pinctrl_reg_cache *cache =
> > pctrl->cache;
> > +                       u32 pfc_val, pfc_mask;
> >
> >                         /* Nothing to do if PFC was not configured before. */
> >                         if (!(cache->pmc[port] & BIT(pin)))
> >                                 continue;
> >
> > +                       pfc_val = readl(pctrl->base + PFC(off));
> > +                       pfc_mask = PFC_MASK << (pin * 4);
> > +                       /* Nothing to do if reset value of the pin is same as cached value */
> > +                       if ((cache->pfc[port] & pfc_mask) == (pfc_val & pfc_mask))
> > +                               continue;
> 
> What if the pin is currently configured for GPIO in the PMC register?

That won't happen due to the check 2 lines above.

> >                         if (!(cache->pmc[port] & BIT(pin)))
> >                                 continue;


Cheers,
Biju