linux-kernel - [PATCH] clk: at91: clk-master: Add check for divide by 3

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Message-ID: <20250908200725.75364-1-Ryan.Wanner@microchip.com>
Date: Mon, 8 Sep 2025 13:07:17 -0700
From: <Ryan.Wanner@...rochip.com>
To: <mturquette@...libre.com>, <sboyd@...nel.org>,
	<nicolas.ferre@...rochip.com>, <alexandre.belloni@...tlin.com>,
	<claudiu.beznea@...on.dev>
CC: <linux-clk@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
	<linux-kernel@...r.kernel.org>, Ryan Wanner <Ryan.Wanner@...rochip.com>
Subject: [PATCH] clk: at91: clk-master: Add check for divide by 3

From: Ryan Wanner <Ryan.Wanner@...rochip.com>

A potential divider for the master clock is div/3. The register
configuration for div/3 is MASTER_PRES_MAX. The current bit shifting
method does not work for this case. Checking for MASTER_PRES_MAX will
ensure the correct decimal value is stored in the system.

Signed-off-by: Ryan Wanner <Ryan.Wanner@...rochip.com>
---
 drivers/clk/at91/clk-master.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
index 7a544e429d34..d5ea2069ec83 100644
--- a/drivers/clk/at91/clk-master.c
+++ b/drivers/clk/at91/clk-master.c
@@ -580,6 +580,9 @@ clk_sama7g5_master_recalc_rate(struct clk_hw *hw,
 {
 	struct clk_master *master = to_clk_master(hw);
 
+	if (master->div == MASTER_PRES_MAX)
+		return DIV_ROUND_CLOSEST_ULL(parent_rate, 3);
+
 	return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div));
 }
 
-- 
2.43.0