linux-kernel - Re: [PATCH v4] PCI: j721e: Fix programming sequence of "strap" settings

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Message-Id: <175733420164.9759.8251040864412190074.b4-ty@kernel.org>
Date: Mon, 08 Sep 2025 17:53:21 +0530
From: Manivannan Sadhasivam <mani@...nel.org>
To: lpieralisi@...nel.org, kwilczynski@...nel.org, robh@...nel.org, 
 bhelgaas@...gle.com, helgaas@...nel.org, kishon@...nel.org, vigneshr@...com, 
 Siddharth Vadapalli <s-vadapalli@...com>
Cc: stable@...r.kernel.org, linux-pci@...r.kernel.org, 
 linux-omap@...r.kernel.org, linux-kernel@...r.kernel.org, 
 linux-arm-kernel@...ts.infradead.org, srk@...com
Subject: Re: [PATCH v4] PCI: j721e: Fix programming sequence of "strap"
 settings


On Mon, 08 Sep 2025 17:38:27 +0530, Siddharth Vadapalli wrote:
> The Cadence PCIe Controller integrated in the TI K3 SoCs supports both
> Root-Complex and Endpoint modes of operation. The Glue Layer allows
> "strapping" the Mode of operation of the Controller, the Link Speed
> and the Link Width. This is enabled by programming the "PCIEn_CTRL"
> register (n corresponds to the PCIe instance) within the CTRL_MMR
> memory-mapped register space. The "reset-values" of the registers are
> also different depending on the mode of operation.
> 
> [...]

Applied, thanks!

[1/1] PCI: j721e: Fix programming sequence of "strap" settings
      commit: f842d3313ba179d4005096357289c7ad09cec575

Best regards,
-- 
Manivannan Sadhasivam <mani@...nel.org>