linux-kernel - Re: [PATCH v6 02/15] x86/mce: Define BSP-only init

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Message-ID: <20250910135323.GC11602@yaz-khff2.amd.com>
Date: Wed, 10 Sep 2025 09:53:23 -0400
From: Yazen Ghannam <yazen.ghannam@....com>
To: Nikolay Borisov <nik.borisov@...e.com>
Cc: x86@...nel.org, Tony Luck <tony.luck@...el.com>,
	"Rafael J. Wysocki" <rafael@...nel.org>,
	linux-kernel@...r.kernel.org, linux-edac@...r.kernel.org,
	Smita.KoralahalliChannabasappa@....com,
	Qiuxu Zhuo <qiuxu.zhuo@...el.com>, linux-acpi@...r.kernel.org
Subject: Re: [PATCH v6 02/15] x86/mce: Define BSP-only init

On Wed, Sep 10, 2025 at 02:47:16PM +0300, Nikolay Borisov wrote:
> 
> 
> On 9/8/25 18:40, Yazen Ghannam wrote:
> > Currently, MCA initialization is executed identically on each CPU as
> > they are brought online. However, a number of MCA initialization tasks
> > only need to be done once.
> > 
> > Define a function to collect all 'global' init tasks and call this from
> > the BSP only. Start with CPU features.
> > 
> > Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@...el.com>
> > Tested-by: Tony Luck <tony.luck@...el.com>
> > Reviewed-by: Tony Luck <tony.luck@...el.com>
> > Signed-off-by: Yazen Ghannam <yazen.ghannam@....com>
> 
> <snip>
> 
> > @@ -2240,6 +2233,27 @@ DEFINE_IDTENTRY_RAW(exc_machine_check)
> >   }
> >   #endif
> > +void mca_bsp_init(struct cpuinfo_x86 *c)
> > +{
> > +	u64 cap;
> > +
> > +	if (!mce_available(c))
> > +		return;
> > +
> > +	mce_flags.overflow_recov = cpu_feature_enabled(X86_FEATURE_OVERFLOW_RECOV);
> > +	mce_flags.succor	 = cpu_feature_enabled(X86_FEATURE_SUCCOR);
> > +	mce_flags.smca		 = cpu_feature_enabled(X86_FEATURE_SMCA);
> > +
> > +	rdmsrq(MSR_IA32_MCG_CAP, cap);
> > +
> > +	/* Use accurate RIP reporting if available. */
> > +	if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
> > +		mca_cfg.rip_msr = MSR_IA32_MCG_EIP;
> > +
> > +	if (cap & MCG_SER_P)
> > +		mca_cfg.ser = 1;
> > +}
> > +
> 
> 
> LGTM
> 
> Reviewed-by: Nikolay Borisov <nik.borisov@...e.com>

Thanks Nikokay for the reviews.

> 
> nit: One question though for those CPUs which consist of P+E cores, is it
> mandated that both types of cores will have identical MCE architecture, I
> assume the x86 world will be a lot more unified than Arm's big.LITTLE ?
> 

I think technically no, they won't be mandated to be identical. We already
have per-CPU feature bits, registers, etc. And in Scalable MCA there are
also per-bank config bits.

However, this doesn't mean we will have different MCE features between
CPUs in a system just yet. The architects do try to make things flexible
and scalable just in case there is a need in the future.

We can code to the architectures and be *mostly* future-proof. But it's
not guaranteed to be without bugs. And it's not guaranteed that every
possible case will be used. 

Do you have any concerns or see any issues with the code today in this
area? Maybe you're thinking we should have per-CPU config for feature
bits? If so, I agree but we don't have a real need today AFAIK.

Maybe others can comment too.

Thanks,
Yazen