linux-kernel - Re: [PATCH v2 2/2] arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes

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Message-ID: <f516f2021e9b1c541575c5f317037873fa2c730a.camel@codeconstruct.com.au>
Date: Wed, 10 Sep 2025 17:26:31 +0930
From: Andrew Jeffery <andrew@...econstruct.com.au>
To: Tomer Maimon <tmaimon77@...il.com>, robh+dt@...nel.org, 
 krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
 avifishman70@...il.com,  tali.perry1@...il.com, joel@....id.au,
 venture@...gle.com, yuenn@...gle.com,  benjaminfair@...gle.com
Cc: openbmc@...ts.ozlabs.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 2/2] arm64: dts: nuvoton: npcm845-evb: Add peripheral
 nodes

On Mon, 2025-09-08 at 15:59 +0300, Tomer Maimon wrote:
> Enable peripheral support for the Nuvoton NPCM845 Evaluation Board by
> adding device nodes for Ethernet controllers, MMC controller, SPI
> controllers, USB device controllers, random number generator, ADC,
> PWM-FAN controller, I2C controllers, and PECI interface.
> Include MDIO nodes for Ethernet PHYs, reserved memory for TIP, and
> aliases for device access.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@...il.com>
> ---
>  .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts  | 439
> ++++++++++++++++++
>  1 file changed, 439 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> index 2638ee1c3846..145a2e599600 100644
> --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> @@ -10,6 +10,42 @@ / {
>  
>         aliases {
>                 serial0 = &serial0;
> +               ethernet1 = &gmac1;
> +               ethernet2 = &gmac2;
> +               ethernet3 = &gmac3;
> +               mdio-gpio0 = &mdio0;
> +               mdio-gpio1 = &mdio1;
> +               fiu0 = &fiu0;
> +               fiu1 = &fiu3;
> +               fiu2 = &fiux;
> +               fiu3 = &fiu1;
> +               i2c0 = &i2c0;
> +               i2c1 = &i2c1;
> +               i2c2 = &i2c2;
> +               i2c3 = &i2c3;
> +               i2c4 = &i2c4;
> +               i2c5 = &i2c5;
> +               i2c6 = &i2c6;
> +               i2c7 = &i2c7;
> +               i2c8 = &i2c8;
> +               i2c9 = &i2c9;
> +               i2c10 = &i2c10;
> +               i2c11 = &i2c11;
> +               i2c12 = &i2c12;
> +               i2c13 = &i2c13;
> +               i2c14 = &i2c14;
> +               i2c15 = &i2c15;
> +               i2c16 = &i2c16;
> +               i2c17 = &i2c17;
> +               i2c18 = &i2c18;
> +               i2c19 = &i2c19;
> +               i2c20 = &i2c20;
> +               i2c21 = &i2c21;
> +               i2c22 = &i2c22;
> +               i2c23 = &i2c23;
> +               i2c24 = &i2c24;
> +               i2c25 = &i2c25;
> +               i2c26 = &i2c26;
>         };
>  
>         chosen {
> @@ -25,12 +61,415 @@ refclk: refclk-25mhz {
>                 clock-frequency = <25000000>;
>                 #clock-cells = <0>;
>         };
> +
> +       reserved-memory {
> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               ranges;
> +
> +               tip_reserved: tip@0 {
> +                       reg = <0x0 0x0 0x0 0x6200000>;
> +               };
> +       };
> +
> +       mdio0: mdio-0 {
> +               compatible = "virtual,mdio-gpio";
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>,
> +                       <&gpio1 26 GPIO_ACTIVE_HIGH>;
> +
> +               phy0: ethernet-phy@0 {
> +                       reg = <0>;
> +               };
> +       };
> +
> +       mdio1: mdio-1 {
> +               compatible = "virtual,mdio-gpio";
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>,
> +                       <&gpio2 28 GPIO_ACTIVE_HIGH>;
> +
> +               phy1: ethernet-phy@0 {
> +                       reg = <0>;
> +               };
> +       };
> +};

By contrast to ordering the DTSI nodes by unit address, for the
referenced nodes that follow here in the DTS, can you please order them
alphabetically? Ordering them by unit address is allowed by the DTS
style guide, but is super tedious to verify. Alphabetical ordering is
also allowed and is straight-forward to enforce:

https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-nodes

Cheers,

Andrew

> +
> +&gmac1 {
> +       phy-mode = "rgmii-id";
> +       snps,eee-force-disable;
> +       status = "okay";
> +};
> +
> +&gmac2 {
> +       phy-mode = "rmii";
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&r1_pins
> +                       &r1oen_pins>;
> +       phy-handle = <&phy0>;
> +       status = "okay";
> +};
> +
> +&gmac3 {
> +       phy-mode = "rmii";
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&r2_pins
> +                       &r2oen_pins>;
> +       phy-handle = <&phy1>;
> +       status = "okay";
>  };
>  
>  &serial0 {
>         status = "okay";
>  };
>  
> +&fiu0 {

*snip*