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Message-ID: <aMDdF7h/YCcVD9oA@Asurada-Nvidia>
Date: Tue, 9 Sep 2025 19:06:15 -0700
From: Nicolin Chen <nicolinc@...dia.com>
To: Balbir Singh <balbirs@...dia.com>
CC: <jgg@...dia.com>, <will@...nel.org>, <robin.murphy@....com>,
	<joro@...tes.org>, <jean-philippe@...aro.org>, <miko.lenczewski@....com>,
	<peterz@...radead.org>, <smostafa@...gle.com>, <kevin.tian@...el.com>,
	<praan@...gle.com>, <linux-arm-kernel@...ts.infradead.org>,
	<iommu@...ts.linux.dev>, <linux-kernel@...r.kernel.org>,
	<patches@...ts.linux.dev>
Subject: Re: [PATCH rfcv2 2/8] iommu/arm-smmu-v3: Explicitly set
 smmu_domain->stage for SVA

On Wed, Sep 10, 2025 at 08:31:43AM +1000, Balbir Singh wrote:
> On 9/9/25 09:26, Nicolin Chen wrote:
> > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> > index cccf8f52ee0d5..0016ec699acfe 100644
> > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> > @@ -3070,6 +3070,9 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
> >  		arm_smmu_install_ste_for_dev(master, &target);
> >  		arm_smmu_clear_cd(master, IOMMU_NO_PASID);
> >  		break;
> > +	default:
> > +		WARN_ON(true);
> 
> WARN_ONCE_ONCE() and shoudn't ret be set to -EINVAL?

I will fix it.

Thanks
Nicolin

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