linux-kernel - Re: [PATCH v2 2/2] arm64: dts: rockchip: Add devicetree for the ROC-RK3588-RT

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <ec8a3649-3f8f-40b7-a534-041b3523efe4@lunn.ch>
Date: Wed, 10 Sep 2025 14:15:33 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Kaison <dkx@...hip.com.cn>
Cc: Rob Herring <robh@...nel.org>, Jimmy Hon <honyuenkwun@...il.com>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Heiko Stuebner <heiko@...ech.de>, Wayne Chou <zxf@...hip.com.cn>,
	Quentin Schulz <quentin.schulz@...rry.de>,
	Dragan Simic <dsimic@...jaro.org>, Jonas Karlman <jonas@...boo.se>,
	FUKAUMI Naoki <naoki@...xa.com>,
	Peter Robinson <pbrobinson@...il.com>, devicetree@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org,
	linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 2/2] arm64: dts: rockchip: Add devicetree for the
 ROC-RK3588-RT

On Wed, Sep 10, 2025 at 10:55:22AM +0800, Kaison wrote:
> hi,
> I'm very sorry. Due to the default configuration of my email, I didn't
> receive your email normally. I have fixed this issue.
> 
> On Tue, 2025-09-09 at 14:31 +0200, Andrew Lunn wrote:
> > > - 2x Gigabit Ethernet, 1x 2.5G Ethernet
> > 
> > I actually only see the 2x 1G. Is the 2.5G not supported yet?
> The 2.5G Ethernet is based on the Realtek RTL8125 network controller of
> PCIe 2.0x1.

Ah, O.K. Maybe add a comment, because i was looking for something
integrated into the SoC, not a PCIe device.

> > > +&gmac0 {
> > > +	clock_in_out = "output";
> > > +	phy-handle = <&rgmii_phy0>;
> > > +	phy-mode = "rgmii-rxid";
> > > +	pinctrl-names = "default";
> > > +	pinctrl-0 = <&gmac0_miim
> > > +		     &gmac0_tx_bus2
> > > +		     &gmac0_rx_bus2
> > > +		     &gmac0_rgmii_clk
> > > +		     &gmac0_rgmii_bus>;
> > > +	tx_delay = <0x47>;
> > 
> > What happened about my comment that "rgmii-rxid" is probably wrong?
> > 
> > If you think it is correct, you should reply with a
> > justification. Maybe PCB is very odd? In which case, a comment would
> > be good to explain who it is odd.
> The Ethernet part of the board is designed with reference to the
> rockchip evb1 board. 
> 
> link: 
> https://github.com/Firefly-rk-linux/docs/blob/rk3588/firefly-public/en/Common/GMAC/Rockchip_Developer_Guide_Linux_GMAC_RGMII_Delayline_EN.pdf
> 
> 
> The document describes the usage of the rgmii-rxid mode:
> 
> When the hardware enables the RX delay of the PHY. Need to turn off the
> RX delay of the GMAC, and the dts configuration mode becomes "rgmii-
> rxid".

Vendors get this wrong as well, and give you bad advice. Please look
at:

https://elixir.bootlin.com/linux/v6.16.5/source/Documentation/devicetree/bindings/net/ethernet-controller.yaml#L264

	Andrew