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Message-ID: <isafba2w6ddl2wqiescae6a5dab66ezuinuq7aaivriz3pnixt@j6ymwk3itcka>
Date: Thu, 11 Sep 2025 22:35:50 +0530
From: Manivannan Sadhasivam <mani@...nel.org>
To: Palash Kambar <quic_pkambar@...cinc.com>
Cc: James.Bottomley@...senpartnership.com, martin.petersen@...cle.com,
linux-arm-msm@...r.kernel.org, linux-scsi@...r.kernel.org, linux-kernel@...r.kernel.org,
quic_nitirawa@...cinc.com
Subject: Re: [PATCH V2] ufs: ufs-qcom: disable lane clocks during phy hibern8
On Tue, Sep 09, 2025 at 11:21:49AM GMT, Palash Kambar wrote:
> Currently, the UFS lane clocks remain enabled even after the link
> enters the Hibern8 state and are only disabled during runtime/system
> suspend.This patch modifies the behavior to disable the lane clocks
> during ufs_qcom_setup_clocks(), which is invoked shortly after the
> link enters Hibern8 via gate work.
>
> While hibern8_notify() offers immediate control, toggling clocks on
> every transition isn't ideal due to varied contexts like clock scaling.
> Since setup_clocks() manages PHY/controller resources and is invoked
> soon after Hibern8 entry, it serves as a central and stable point
> for clock gating.
>
> Signed-off-by: Palash Kambar <quic_pkambar@...cinc.com>
Reviewed-by: Manivannan Sadhasivam <mani@...nel.org>
- Mani
>
> ---
> changes from V1:
> 1) Addressed Manivannan's comments and added detailed justification.
> ---
> drivers/ufs/host/ufs-qcom.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index c0761ccc1381..83ad25ce053d 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -1092,6 +1092,13 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
> case PRE_CHANGE:
> if (on) {
> ufs_qcom_icc_update_bw(host);
> + if (ufs_qcom_is_link_hibern8(hba)) {
> + err = ufs_qcom_enable_lane_clks(host);
> + if (err) {
> + dev_err(hba->dev, "enable lane clks failed, ret=%d\n", err);
> + return err;
> + }
> + }
> } else {
> if (!ufs_qcom_is_link_active(hba)) {
> /* disable device ref_clk */
> @@ -1105,6 +1112,9 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
> if (ufshcd_is_hs_mode(&hba->pwr_info))
> ufs_qcom_dev_ref_clk_ctrl(host, true);
> } else {
> + if (ufs_qcom_is_link_hibern8(hba))
> + ufs_qcom_disable_lane_clks(host);
> +
> ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MIN][0][0].mem_bw,
> ufs_qcom_bw_table[MODE_MIN][0][0].cfg_bw);
> }
> --
> 2.34.1
>
--
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