Message-ID: <8a4272f7-0d22-43f0-993b-6d53172b7f65@amd.com>
Date: Thu, 11 Sep 2025 10:07:39 +0530
From: K Prateek Nayak <kprateek.nayak@....com>
To: Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>,
	Borislav Petkov <bp@...en8.de>, Dave Hansen <dave.hansen@...ux.intel.com>,
	Sean Christopherson <seanjc@...gle.com>, Paolo Bonzini <pbonzini@...hat.com>,
	Jonathan Corbet <corbet@....net>, <x86@...nel.org>
CC: Naveen rao <naveen.rao@....com>, Sairaj Kodilkar <sarunkod@....com>, "H.
 Peter Anvin" <hpa@...or.com>, "Peter Zijlstra (Intel)"
	<peterz@...radead.org>, "Xin Li (Intel)" <xin@...or.com>, Pawan Gupta
	<pawan.kumar.gupta@...ux.intel.com>, <linux-kernel@...r.kernel.org>,
	<kvm@...r.kernel.org>, Mario Limonciello <mario.limonciello@....com>,
	"Gautham R. Shenoy" <gautham.shenoy@....com>, Babu Moger
	<babu.moger@....com>, Suravee Suthikulpanit <suravee.suthikulpanit@....com>,
	<stable@...r.kernel.org>, Naveen N Rao <naveen@...nel.org>
Subject: Re: [PATCH v5 1/4] x86/cpu/topology: Always try
 cpu_parse_topology_ext() on AMD/Hygon

Hello Thomas,

On 9/11/2025 1:40 AM, Thomas Gleixner wrote:
> On Mon, Sep 01 2025 at 17:04, K. Prateek Nayak wrote:
>> Unconditionally call cpu_parse_topology_ext() on AMD and Hygon
>> processors to first parse the topology using the XTOPOLOGY leaves
>> (0x80000026 / 0xb) before using the TOPOEXT leaf (0x8000001e).
>>
>> While at it, break down the single large comment in parse_topology_amd()
>> to better highlight the purpose of each CPUID leaf.
>>
>> Cc: stable@...r.kernel.org # Only v6.9 and above; Depends on x86 topology rewrite
>> Link: https://lore.kernel.org/lkml/1529686927-7665-1-git-send-email-suravee.suthikulpanit@amd.com/ [1]
>> Link: https://lore.kernel.org/lkml/20080818181435.523309000@linux-os.sc.intel.com/ [2]
>> Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 [3]
>> Suggested-by: Naveen N Rao (AMD) <naveen@...nel.org>
>> Fixes: 3986a0a805e6 ("x86/CPU/AMD: Derive CPU topology from CPUID function 0xB when available")
>> Signed-off-by: K Prateek Nayak <kprateek.nayak@....com>
>> ---
>> Changelog v4..v5:
>>
>> o Made a note on only targeting versions >= v6.9 for stable backports
>>   since the fix depends on the x86 topology rewrite. (Boris)
> 
> Shouldn't that be backported? I think so, so leave that v6.9 and above
> comment out. The stable folks will notice that it does not apply to pre
> 6.9 kernels and send you a nice email asking you to provide a solution
> for pre 6.9 stable kernels.

Ack! Since this is already in tip:x86/urgent as commit cba4262a19af
("x86/cpu/topology: Always try cpu_parse_topology_ext() on AMD/Hygon")
let me know if I should resend it or that comment can be zapped
in-place.

I can also send out a separate patch targeting stable with the intended
changes. Since we are on the topic, here is the patch I would have sent
out to stable:

(Note: Only tested on top of v6.6.105 stable on a Zen3 machine; no
 changes found in /sys/devices/system/cpu/cpu*/topology/* with the patch
 applied on top)

From: K Prateek Nayak <kprateek.nayak@....com>
Subject: [PATCH stable] x86/cpu/amd: Always try detect_extended_topology()
 on AMD processors

commit cba4262a19afae21665ee242b3404bcede5a94d7 upstream.

Support for parsing the topology on AMD/Hygon processors using CPUID leaf 0xb
was added in

  3986a0a805e6 ("x86/CPU/AMD: Derive CPU topology from CPUID function 0xB when available").

In an effort to keep all the topology parsing bits in one place, this commit
also introduced a pseudo dependency on the TOPOEXT feature to parse the CPUID
leaf 0xb.

The TOPOEXT feature (CPUID 0x80000001 ECX[22]) advertises the support for
Cache Properties leaf 0x8000001d and the CPUID leaf 0x8000001e EAX for
"Extended APIC ID" however support for 0xb was introduced alongside the x2APIC
support not only on AMD [1], but also historically on x86 [2].

The support for the 0xb leaf is expected to be confirmed by ensuring

  leaf <= max supported cpuid_level

and then parsing the level 0 of the leaf to confirm EBX[15:0]
(LogProcAtThisLevel) is non-zero as stated in the definition of
"CPUID_Fn0000000B_EAX_x00 [Extended Topology Enumeration]
(Core::X86::Cpuid::ExtTopEnumEax0)" in Processor Programming Reference (PPR)
for AMD Family 19h Model 01h Rev B1 Vol1 [3] Sec. 2.1.15.1 "CPUID Instruction
Functions".

This has not been a problem on baremetal platforms since support for TOPOEXT
(Fam 0x15 and later) predates the support for CPUID leaf 0xb (Fam 0x17[Zen2]
and later), however, for AMD guests on QEMU, the "x2apic" feature can be
enabled independent of the "topoext" feature where QEMU expects topology and
the initial APICID to be parsed using the CPUID leaf 0xb (especially when
number of cores > 255) which is populated independent of the "topoext" feature
flag.

Unconditionally call detect_extended_topology() on AMD processors to first
parse the topology using the extended topology leaf 0xb before using the
TOPOEXT leaf (0x8000001e).

Fixes: 3986a0a805e6 ("x86/CPU/AMD: Derive CPU topology from CPUID function 0xB when available")
Suggested-by: Naveen N Rao (AMD) <naveen@...nel.org>
Signed-off-by: K Prateek Nayak <kprateek.nayak@....com>
Link: https://lore.kernel.org/lkml/1529686927-7665-1-git-send-email-suravee.suthikulpanit@amd.com/ [1]
Link: https://lore.kernel.org/lkml/20080818181435.523309000@linux-os.sc.intel.com/ [2]
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 [3]
---
For stable maintainers,

The original changes from commit cba4262a19af ("x86/cpu/topology: Always try
cpu_parse_topology_ext() on AMD/Hygon") cannot be easily backported due to the
extensive x86 topology rewrite in v6.9.

This patch cleanly applies on top of all stable kernels from v6.6.y to v5.4.y.
Boris' S-o-b from commit commit cba4262a19af has been dropped since the changes
on top of the stable kernels are slightly different.
---
 arch/x86/kernel/cpu/amd.c | 37 ++++++++++++++++++++++---------------
 1 file changed, 22 insertions(+), 15 deletions(-)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 864d62e94614..33d8bbdd7b69 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -391,34 +391,41 @@ static void legacy_fixup_core_id(struct cpuinfo_x86 *c)
  */
 static void amd_get_topology(struct cpuinfo_x86 *c)
 {
+	/*
+	 * Try to get the topology information from the 0xb leaf first.
+	 * If detect_extended_topology() returns 0, parsing was successful
+	 * and APIC ID, cpu_core_id, cpu_die_id, phys_proc_id, and
+	 * __max_die_per_package are already populated.
+	 */
+	bool has_extended_topology = !detect_extended_topology(c);
 	int cpu = smp_processor_id();
 
+	if (has_extended_topology)
+		c->x86_coreid_bits = get_count_order(c->x86_max_cores);
+
 	/* get information required for multi-node processors */
 	if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
-		int err;
 		u32 eax, ebx, ecx, edx;
 
 		cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
 
-		c->cpu_die_id  = ecx & 0xff;
-
 		if (c->x86 == 0x15)
 			c->cu_id = ebx & 0xff;
 
-		if (c->x86 >= 0x17) {
-			c->cpu_core_id = ebx & 0xff;
-
-			if (smp_num_siblings > 1)
-				c->x86_max_cores /= smp_num_siblings;
-		}
-
 		/*
-		 * In case leaf B is available, use it to derive
-		 * topology information.
+		 * If the extended topology leaf 0xb leaf doesn't exits,
+		 * derive CORE and DIE information from the 0x8000001e leaf.
 		 */
-		err = detect_extended_topology(c);
-		if (!err)
-			c->x86_coreid_bits = get_count_order(c->x86_max_cores);
+		if (!has_extended_topology) {
+			c->cpu_die_id  = ecx & 0xff;
+
+			if (c->x86 >= 0x17) {
+				c->cpu_core_id = ebx & 0xff;
+
+				if (smp_num_siblings > 1)
+					c->x86_max_cores /= smp_num_siblings;
+			}
+		}
 
 		cacheinfo_amd_init_llc_id(c, cpu);
 

base-commit: fe9731e100041bb2cc186717bde3e05ca175623b
--

Let me know what you think.

-- 
Thanks and Regards,
Prateek

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