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Message-ID: <87ikhnomiy.fsf@BLaptop.bootlin.com>
Date: Fri, 12 Sep 2025 14:58:29 +0200
From: Gregory CLEMENT <gregory.clement@...tlin.com>
To: Josua Mayer <josua@...id-run.com>, Andrew Lunn <andrew@...n.ch>,
Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>, Rob Herring
<robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, Frank Wunderlich <frank-w@...lic-files.de>
Cc: linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Josua Mayer <josua@...id-run.com>,
stable@...r.kernel.org
Subject: Re: [PATCH v2 3/4] arm64: dts: marvell: cn9132-clearfog: fix
multi-lane pci x2 and x4 ports
Josua Mayer <josua@...id-run.com> writes:
> The mvebu-comphy driver does not currently know how to pass correct
> lane-count to ATF while configuring the serdes lanes.
>
> This causes the system to hard reset during reconfiguration, if a pci
> card is present and has established a link during bootloader.
>
> Remove the comphy handles from the respective pci nodes to avoid runtime
> reconfiguration, relying solely on bootloader configuration - while
> avoiding the hard reset.
>
> When bootloader has configured the lanes correctly, the pci ports are
> functional under Linux.
>
> This issue may be addressed in the comphy driver at a future point.
>
> Fixes: e9ff907f4076 ("arm64: dts: add description for solidrun cn9132 cex7 module and clearfog board")
> Cc: <stable@...r.kernel.org>
> Signed-off-by: Josua Mayer <josua@...id-run.com>
Applied on mvebu/fixes
Thanks,
Gregory
> ---
> arch/arm64/boot/dts/marvell/cn9132-clearfog.dts | 16 ++++++++++++++--
> 1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts b/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts
> index 115c55d73786e2b9265e1caa4c62ee26f498fb41..6f237d3542b9102695f8a48457f43340da994a2c 100644
> --- a/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts
> +++ b/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts
> @@ -413,7 +413,13 @@ fixed-link {
> /* SRDS #0,#1,#2,#3 - PCIe */
> &cp0_pcie0 {
> num-lanes = <4>;
> - phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>;
> + /*
> + * The mvebu-comphy driver does not currently know how to pass correct
> + * lane-count to ATF while configuring the serdes lanes.
> + * Rely on bootloader configuration only.
> + *
> + * phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>;
> + */
> status = "okay";
> };
>
> @@ -475,7 +481,13 @@ &cp1_eth0 {
> /* SRDS #0,#1 - PCIe */
> &cp1_pcie0 {
> num-lanes = <2>;
> - phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>;
> + /*
> + * The mvebu-comphy driver does not currently know how to pass correct
> + * lane-count to ATF while configuring the serdes lanes.
> + * Rely on bootloader configuration only.
> + *
> + * phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>;
> + */
> status = "okay";
> };
>
>
> --
> 2.51.0
>
>
--
Grégory CLEMENT, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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