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Message-ID: <20250912131438.74900e88@canb.auug.org.au>
Date: Fri, 12 Sep 2025 13:14:38 +1000
From: Stephen Rothwell <sfr@...b.auug.org.au>
To: Sean Christopherson <seanjc@...gle.com>
Cc: Dave Hansen <dave.hansen@...ux.intel.com>, Linux Kernel Mailing List
 <linux-kernel@...r.kernel.org>, Linux Next Mailing List
 <linux-next@...r.kernel.org>, Pawan Gupta
 <pawan.kumar.gupta@...ux.intel.com>, Xin Li <xin@...or.com>
Subject: linux-next: manual merge of the kvm-x86 tree with Linus' tree

Hi all,

Today's linux-next merge of the kvm-x86 tree got a conflict in:

  arch/x86/include/asm/cpufeatures.h

between commit:

  2f8f173413f1 ("x86/vmscape: Add conditional IBPB mitigation")

from Linus' tree and commit:

  3c7cb8414533 ("x86/cpufeatures: Add a CPU feature bit for MSR immediate form instructions")

from the kvm-x86 tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc arch/x86/include/asm/cpufeatures.h
index 751ca35386b0,8738bd783de2..000000000000
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@@ -495,7 -496,7 +496,8 @@@
  #define X86_FEATURE_TSA_SQ_NO		(21*32+11) /* AMD CPU not vulnerable to TSA-SQ */
  #define X86_FEATURE_TSA_L1_NO		(21*32+12) /* AMD CPU not vulnerable to TSA-L1 */
  #define X86_FEATURE_CLEAR_CPU_BUF_VM	(21*32+13) /* Clear CPU buffers using VERW before VMRUN */
 -#define X86_FEATURE_MSR_IMM		(21*32+14) /* MSR immediate form instructions */
 +#define X86_FEATURE_IBPB_EXIT_TO_USER	(21*32+14) /* Use IBPB on exit-to-userspace, see VMSCAPE bug */
++#define X86_FEATURE_MSR_IMM		(21*32+15) /* MSR immediate form instructions */
  
  /*
   * BUG word(s)

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