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Message-ID: <fb81c74a-d53d-4917-9516-9854e825913a@gmail.com>
Date: Fri, 12 Sep 2025 16:19:06 +0200
From: Matthias Brugger <matthias.bgg@...il.com>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
linux-mediatek@...ts.infradead.org, robh@...nel.org
Cc: herbert@...dor.apana.org.au, davem@...emloft.net, krzk+dt@...nel.org,
conor+dt@...nel.org, chunkuang.hu@...nel.org, p.zabel@...gutronix.de,
airlied@...il.com, simona@...ll.ch, maarten.lankhorst@...ux.intel.com,
mripard@...nel.org, tzimmermann@...e.de, jassisinghbrar@...il.com,
mchehab@...nel.org, chunfeng.yun@...iatek.com, vkoul@...nel.org,
kishon@...nel.org, sean.wang@...nel.org, linus.walleij@...aro.org,
lgirdwood@...il.com, broonie@...nel.org, andersson@...nel.org,
mathieu.poirier@...aro.org, daniel.lezcano@...aro.org, tglx@...utronix.de,
atenart@...nel.org, jitao.shi@...iatek.com, ck.hu@...iatek.com,
houlong.wei@...iatek.com, kyrie.wu@...iatek.corp-partner.google.com,
andy.teng@...iatek.com, tinghan.shen@...iatek.com, jiaxin.yu@...iatek.com,
shane.chien@...iatek.com, olivia.wen@...iatek.com, granquet@...libre.com,
eugen.hristev@...aro.org, arnd@...db.de, sam.shih@...iatek.com,
jieyy.yang@...iatek.com, frank-w@...lic-files.de, mwalle@...nel.org,
fparent@...libre.com, linux-crypto@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
dri-devel@...ts.freedesktop.org, linux-media@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-phy@...ts.infradead.org,
linux-gpio@...r.kernel.org, linux-remoteproc@...r.kernel.org,
linux-sound@...r.kernel.org
Subject: Re: [PATCH 32/38] arm64: dts: mediatek: mt8183: Migrate to display
controller OF graph
On 24/07/2025 10:39, AngeloGioacchino Del Regno wrote:
> The display related IPs in MT8183 are flexible and support being
> interconnected with different instances of DDP IPs forming a full
> Display Data Path that ends with an actual display output, which
> is board specific.
>
> Add a common graph in the main mt8183.dtsi devicetree, which is
> shared between all of the currently supported boards, and do it
> such that only a very minimal amount of changes are needed to
> each board - the only required change was done in mt8183-pumpkin,
> using a phandle to assign the display to DPI0.
>
> All boards featuring any display functionality will extend this
> common graph to hook the display controller of the SoC to their
> specific output port(s).
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Applied, thanks
> ---
> .../boot/dts/mediatek/mt8183-pumpkin.dts | 8 +-
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 239 +++++++++++++++++-
> 2 files changed, 238 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
> index d5fcb010e1ac..cf1d33384bf0 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
> @@ -531,10 +531,8 @@ &dpi0 {
> pinctrl-0 = <&dpi_func_pins>;
> pinctrl-1 = <&dpi_idle_pins>;
> status = "okay";
> +};
>
> - port {
> - dpi_out: endpoint {
> - remote-endpoint = <&it66121_in>;
> - };
> - };
> +&dpi_out {
> + remote-endpoint = <&it66121_in>;
> };
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index 3c1fe80e64b9..960d8955d018 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -1667,6 +1667,21 @@ mmsys: syscon@...00000 {
> mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
> <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
> mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> +
> + port {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mmsys_ep_main: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&ovl0_in>;
> + };
> +
> + mmsys_ep_ext: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&ovl_2l1_in>;
> + };
> + };
> };
>
> dma-controller0@...01000 {
> @@ -1733,6 +1748,25 @@ ovl0: ovl@...08000 {
> clocks = <&mmsys CLK_MM_DISP_OVL0>;
> iommus = <&iommu M4U_PORT_DISP_OVL0>;
> mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + ovl0_in: endpoint {
> + remote-endpoint = <&mmsys_ep_main>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + ovl0_out: endpoint {
> + remote-endpoint = <&ovl_2l0_in>;
> + };
> + };
> + };
> };
>
> ovl_2l0: ovl@...09000 {
> @@ -1743,6 +1777,25 @@ ovl_2l0: ovl@...09000 {
> clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
> mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + ovl_2l0_in: endpoint {
> + remote-endpoint = <&ovl0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + ovl_2l0_out: endpoint {
> + remote-endpoint = <&rdma0_in>;
> + };
> + };
> + };
> };
>
> ovl_2l1: ovl@...0a000 {
> @@ -1753,6 +1806,25 @@ ovl_2l1: ovl@...0a000 {
> clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
> iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>;
> mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + ovl_2l1_in: endpoint {
> + remote-endpoint = <&mmsys_ep_ext>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + ovl_2l1_out: endpoint {
> + remote-endpoint = <&rdma1_in>;
> + };
> + };
> + };
> };
>
> rdma0: rdma@...0b000 {
> @@ -1764,6 +1836,25 @@ rdma0: rdma@...0b000 {
> iommus = <&iommu M4U_PORT_DISP_RDMA0>;
> mediatek,rdma-fifo-size = <5120>;
> mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + rdma0_in: endpoint {
> + remote-endpoint = <&ovl_2l0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + rdma0_out: endpoint {
> + remote-endpoint = <&color0_in>;
> + };
> + };
> + };
> };
>
> rdma1: rdma@...0c000 {
> @@ -1775,6 +1866,25 @@ rdma1: rdma@...0c000 {
> iommus = <&iommu M4U_PORT_DISP_RDMA1>;
> mediatek,rdma-fifo-size = <2048>;
> mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + rdma1_in: endpoint {
> + remote-endpoint = <&ovl_2l1_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + rdma1_out: endpoint {
> + remote-endpoint = <&dpi_in>;
> + };
> + };
> + };
> };
>
> color0: color@...0e000 {
> @@ -1785,6 +1895,25 @@ color0: color@...0e000 {
> power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + color0_in: endpoint {
> + remote-endpoint = <&rdma0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + color0_out: endpoint {
> + remote-endpoint = <&ccorr0_in>;
> + };
> + };
> + };
> };
>
> ccorr0: ccorr@...0f000 {
> @@ -1794,6 +1923,25 @@ ccorr0: ccorr@...0f000 {
> power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + ccorr0_in: endpoint {
> + remote-endpoint = <&color0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + ccorr0_out: endpoint {
> + remote-endpoint = <&aal0_in>;
> + };
> + };
> + };
> };
>
> aal0: aal@...10000 {
> @@ -1803,6 +1951,25 @@ aal0: aal@...10000 {
> power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_AAL0>;
> mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + aal0_in: endpoint {
> + remote-endpoint = <&ccorr0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + aal0_out: endpoint {
> + remote-endpoint = <&gamma0_in>;
> + };
> + };
> + };
> };
>
> gamma0: gamma@...11000 {
> @@ -1812,6 +1979,25 @@ gamma0: gamma@...11000 {
> power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + gamma0_in: endpoint {
> + remote-endpoint = <&aal0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + gamma0_out: endpoint {
> + remote-endpoint = <&dither0_in>;
> + };
> + };
> + };
> };
>
> dither0: dither@...12000 {
> @@ -1821,6 +2007,25 @@ dither0: dither@...12000 {
> power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dither0_in: endpoint {
> + remote-endpoint = <&gamma0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dither0_out: endpoint {
> + remote-endpoint = <&dsi_in>;
> + };
> + };
> + };
> };
>
> dsi0: dsi@...14000 {
> @@ -1837,8 +2042,21 @@ dsi0: dsi@...14000 {
> phy-names = "dphy";
> status = "disabled";
>
> - port {
> - dsi_out: endpoint { };
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi_in: endpoint {
> + remote-endpoint = <&dither0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi_out: endpoint { };
> + };
> };
> };
>
> @@ -1853,8 +2071,21 @@ dpi0: dpi@...15000 {
> clock-names = "pixel", "engine", "pll";
> status = "disabled";
>
> - port {
> - dpi_out: endpoint { };
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dpi_in: endpoint {
> + remote-endpoint = <&rdma1_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dpi_out: endpoint { };
> + };
> };
> };
>
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