linux-kernel - Re: [PATCH 3/3] riscv: dts: thead: add zfh for th1520

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Message-ID: <20250912-verdict-croon-81ac20e5b621@spud>
Date: Fri, 12 Sep 2025 18:59:08 +0100
From: Conor Dooley <conor@...nel.org>
To: Han Gao <rabenda.cn@...il.com>
Cc: devicetree@...r.kernel.org, Drew Fustini <fustini@...nel.org>,
	Guo Ren <guoren@...nel.org>, Fu Wei <wefu@...hat.com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>, Alexandre Ghiti <alex@...ti.fr>,
	linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
	Han Gao <gaohan@...as.ac.cn>
Subject: Re: [PATCH 3/3] riscv: dts: thead: add zfh for th1520

On Fri, Sep 12, 2025 at 02:45:28AM +0800, Han Gao wrote:
> th1520 support Zfh ISA extension [1].
> 
> Link: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1737721869472/%E7%8E%84%E9%93%81C910%E4%B8%8EC920R1S6%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C%28xrvm%29_20250124.pdf [1]

Could you please cite the section that this is detailed in?

> 
> Signed-off-by: Han Gao <rabenda.cn@...il.com>
> Signed-off-by: Han Gao <gaohan@...as.ac.cn>
> ---
>  arch/riscv/boot/dts/thead/th1520.dtsi | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> index 7f07688aa964..2075bb969c2f 100644
> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -26,7 +26,7 @@ c910_0: cpu@0 {
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>  					       "ziccrse", "zicntr", "zicsr",
> -					       "zifencei", "zihpm",
> +					       "zifencei", "zihpm", "zfh",
>  					       "xtheadvector";
>  			thead,vlenb = <16>;
>  			reg = <0>;
> @@ -53,7 +53,7 @@ c910_1: cpu@1 {
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>  					       "ziccrse", "zicntr", "zicsr",
> -					       "zifencei", "zihpm",
> +					       "zifencei", "zihpm", "zfh",
>  					       "xtheadvector";
>  			thead,vlenb = <16>;
>  			reg = <1>;
> @@ -80,7 +80,7 @@ c910_2: cpu@2 {
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>  					       "ziccrse", "zicntr", "zicsr",
> -					       "zifencei", "zihpm",
> +					       "zifencei", "zihpm", "zfh",
>  					       "xtheadvector";
>  			thead,vlenb = <16>;
>  			reg = <2>;
> @@ -107,7 +107,7 @@ c910_3: cpu@3 {
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>  					       "ziccrse", "zicntr", "zicsr",
> -					       "zifencei", "zihpm",
> +					       "zifencei", "zihpm", "zfh",
>  					       "xtheadvector";
>  			thead,vlenb = <16>;
>  			reg = <3>;
> -- 
> 2.47.3
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@...ts.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

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