linux-kernel - RE: [EXTERNAL] [PATCH v5 03/10] dt-bindings: reserved-memory: Wakeup Mailbox for Intel processors

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Message-ID:
 <DS3PR21MB58787CD89E8A90B2C076398BBF08A@DS3PR21MB5878.namprd21.prod.outlook.com>
Date: Fri, 12 Sep 2025 20:39:37 +0000
From: Dexuan Cui <decui@...rosoft.com>
To: Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>, "x86@...nel.org"
	<x86@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
	<conor+dt@...nel.org>, Rob Herring <robh@...nel.org>, KY Srinivasan
	<kys@...rosoft.com>, Haiyang Zhang <haiyangz@...rosoft.com>, Wei Liu
	<wei.liu@...nel.org>, Michael Kelley <mhklinux@...look.com>, "Rafael J.
 Wysocki" <rafael@...nel.org>
CC: "ssengar@...ux.microsoft.com" <ssengar@...ux.microsoft.com>, Chris Oo
	<cho@...rosoft.com>, "Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>,
	"linux-hyperv@...r.kernel.org" <linux-hyperv@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-acpi@...r.kernel.org" <linux-acpi@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, Ricardo Neri
	<ricardo.neri@...el.com>, Yunhong Jiang <yunhong.jiang@...ux.intel.com>
Subject: RE: [EXTERNAL] [PATCH v5 03/10] dt-bindings: reserved-memory: Wakeup
 Mailbox for Intel processors

> From: Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>
> Sent: Friday, June 27, 2025 8:35 PM
> [...]
> Add DeviceTree bindings to enumerate the wakeup mailbox used in platform
> firmware for Intel processors.
> 
> x86 platforms commonly boot secondary CPUs using an INIT assert, de-assert
> followed by Start-Up IPI messages. The wakeup mailbox can be used when this
> mechanism is unavailable.
> 
> The wakeup mailbox offers more control to the operating system to boot
> secondary CPUs than a spin-table. It allows the reuse of same wakeup vector
> for all CPUs while maintaining control over which CPUs to boot and when.
> While it is possible to achieve the same level of control using a spin-
> table, it would require to specify a separate `cpu-release-addr` for each
> secondary CPU.
> 
> The operation and structure of the mailbox is described in the
> Multiprocessor Wakeup Structure defined in the ACPI specification. Note
> that this structure does not specify how to publish the mailbox to the
> operating system (ACPI-based platform firmware uses a separate table). No
> ACPI table is needed in DeviceTree-based firmware to enumerate the mailbox.
> 
> Add a `compatible` property that the operating system can use to discover
> the mailbox. Nodes wanting to refer to the reserved memory usually define a
> `memory-region` property. /cpus/cpu* nodes would want to refer to the
> mailbox, but they do not have such property defined in the DeviceTree
> specification. Moreover, it would imply that there is a memory region per
> CPU.
> 
> Co-developed-by: Yunhong Jiang <yunhong.jiang@...ux.intel.com>
> Signed-off-by: Yunhong Jiang <yunhong.jiang@...ux.intel.com>
> Signed-off-by: Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>
> ---

LGTM

Reviewed-by: Dexuan Cui <decui@...rosoft.com>