linux-kernel - Re: [patch V4 26/36] rseq: Optimize event setting

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Message-ID: <87jz24qhrr.ffs@tglx>
Date: Fri, 12 Sep 2025 08:58:16 +0200
From: Thomas Gleixner <tglx@...utronix.de>
To: Mathieu Desnoyers <mathieu.desnoyers@...icios.com>, LKML
 <linux-kernel@...r.kernel.org>
Cc: Michael Jeanson <mjeanson@...icios.com>, Jens Axboe <axboe@...nel.dk>,
 Peter Zijlstra <peterz@...radead.org>, "Paul E. McKenney"
 <paulmck@...nel.org>, Boqun Feng <boqun.feng@...il.com>, Paolo Bonzini
 <pbonzini@...hat.com>, Sean Christopherson <seanjc@...gle.com>, Wei Liu
 <wei.liu@...nel.org>, Dexuan Cui <decui@...rosoft.com>, x86@...nel.org,
 Arnd Bergmann <arnd@...db.de>, Heiko Carstens <hca@...ux.ibm.com>,
 Christian Borntraeger <borntraeger@...ux.ibm.com>, Sven Schnelle
 <svens@...ux.ibm.com>, Huacai Chen <chenhuacai@...nel.org>, Paul Walmsley
 <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>
Subject: Re: [patch V4 26/36] rseq: Optimize event setting

On Thu, Sep 11 2025 at 13:15, Mathieu Desnoyers wrote:
> On 2025-09-11 12:06, Thomas Gleixner wrote:
>> On Thu, Sep 11 2025 at 10:03, Mathieu Desnoyers wrote:
>>> On 2025-09-08 17:32, Thomas Gleixner wrote:
>>>>    static inline void rseq_handle_notify_resume(struct pt_regs *regs)
>>>>    {
>>>> -	if (current->rseq.event.has_rseq)
>>>> +	/* '&' is intentional to spare one conditional branch */
>>>> +	if (current->rseq.event.sched_switch & current->rseq.event.has_rseq)
>>>
>>> I wonder.. except for the corner case of rseq unregistration,
>>> when can we have sched_switch set but not has_rseq ?
>>>
>>> We could remove a load from the fast path and the AND if we
>>> clear the sched_switch flag on rseq unregistration.
>> 
>> We probably could. Though I doubt it matters much and I opted for
>> correctness instead of premature optimization.
> Note that this concerns code that documents an explicit " & " as
> intentional to spare a branch, which led me to assume that optimizing
> it was important.

Correct. Optimization and correctness are not mutually exclusive and it
was an obvious optimization to spare the second branch which the
compiler is forced to emit with &&.

A load/AND from them same cache line is definitely cheaper than an extra
conditional branch.

I'm happy to look into that once the dust has settled...

Thanks,

        tglx