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Message-ID: <04e75c1a-7040-403a-84be-82ff2d9f2544@gmail.com>
Date: Fri, 12 Sep 2025 14:09:10 +0200
From: Matthias Brugger <matthias.bgg@...il.com>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
linux-mediatek@...ts.infradead.org, robh@...nel.org
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Subject: Re: [PATCH 04/38] ASoC: dt-bindings: mt8192-afe-pcm: Fix clocks and
clock-names
On 24/07/2025 10:38, AngeloGioacchino Del Regno wrote:
> Both clocks and clock-names are missing (a lot of) entries: add
> all the used audio clocks and their description and also fix the
> example node.
You forgot to fix the example node.
Matthias
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
> ---
> .../bindings/sound/mt8192-afe-pcm.yaml | 106 +++++++++++++++++-
> 1 file changed, 104 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> index 8ddf49b0040d..96ee0a47360d 100644
> --- a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> +++ b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> @@ -47,16 +47,118 @@ properties:
> - description: AFE clock
> - description: ADDA DAC clock
> - description: ADDA DAC pre-distortion clock
> - - description: audio infra sys clock
> - - description: audio infra 26M clock
> + - description: ADDA ADC clock
> + - description: ADDA6 ADC clock
> + - description: Audio low-jitter 22.5792m clock
> + - description: Audio low-jitter 24.576m clock
> + - description: Audio PLL1 tuner clock
> + - description: Audio PLL2 tuner clock
> + - description: Audio Time-Division Multiplexing interface clock
> + - description: ADDA ADC Sine Generator clock
> + - description: audio Non-LE clock
> + - description: Audio DAC High-Resolution clock
> + - description: Audio High-Resolution ADC clock
> + - description: Audio High-Resolution ADC SineGen clock
> + - description: Audio ADDA6 High-Resolution ADC clock
> + - description: Tertiary ADDA DAC clock
> + - description: Tertiary ADDA DAC pre-distortion clock
> + - description: Tertiary ADDA DAC Sine Generator clock
> + - description: Tertiary ADDA DAC High-Resolution clock
> + - description: Audio infra sys clock
> + - description: Audio infra 26M clock
> + - description: Mux for audio clock
> + - description: Mux for audio internal bus clock
> + - description: Mux main divider by 4
> + - description: Primary audio mux
> + - description: Primary audio PLL
> + - description: Secondary audio mux
> + - description: Secondary audio PLL
> + - description: Primary audio en-generator clock
> + - description: Primary PLL divider by 4 for IEC
> + - description: Secondary audio en-generator clock
> + - description: Secondary PLL divider by 4 for IEC
> + - description: Mux selector for I2S port 0
> + - description: Mux selector for I2S port 1
> + - description: Mux selector for I2S port 2
> + - description: Mux selector for I2S port 3
> + - description: Mux selector for I2S port 4
> + - description: Mux selector for I2S port 5
> + - description: Mux selector for I2S port 6
> + - description: Mux selector for I2S port 7
> + - description: Mux selector for I2S port 8
> + - description: Mux selector for I2S port 9
> + - description: APLL1 and APLL2 divider for I2S port 0
> + - description: APLL1 and APLL2 divider for I2S port 1
> + - description: APLL1 and APLL2 divider for I2S port 2
> + - description: APLL1 and APLL2 divider for I2S port 3
> + - description: APLL1 and APLL2 divider for I2S port 4
> + - description: APLL1 and APLL2 divider for IEC
> + - description: APLL1 and APLL2 divider for I2S port 5
> + - description: APLL1 and APLL2 divider for I2S port 6
> + - description: APLL1 and APLL2 divider for I2S port 7
> + - description: APLL1 and APLL2 divider for I2S port 8
> + - description: APLL1 and APLL2 divider for I2S port 9
> + - description: Top mux for audio subsystem
> + - description: 26MHz clock for audio subsystem
>
> clock-names:
> items:
> - const: aud_afe_clk
> - const: aud_dac_clk
> - const: aud_dac_predis_clk
> + - const: aud_adc_clk
> + - const: aud_adda6_adc_clk
> + - const: aud_apll22m_clk
> + - const: aud_apll24m_clk
> + - const: aud_apll1_tuner_clk
> + - const: aud_apll2_tuner_clk
> + - const: aud_tdm_clk
> + - const: aud_tml_clk
> + - const: aud_nle
> + - const: aud_dac_hires_clk
> + - const: aud_adc_hires_clk
> + - const: aud_adc_hires_tml
> + - const: aud_adda6_adc_hires_clk
> + - const: aud_3rd_dac_clk
> + - const: aud_3rd_dac_predis_clk
> + - const: aud_3rd_dac_tml
> + - const: aud_3rd_dac_hires_clk
> - const: aud_infra_clk
> - const: aud_infra_26m_clk
> + - const: top_mux_audio
> + - const: top_mux_audio_int
> + - const: top_mainpll_d4_d4
> + - const: top_mux_aud_1
> + - const: top_apll1_ck
> + - const: top_mux_aud_2
> + - const: top_apll2_ck
> + - const: top_mux_aud_eng1
> + - const: top_apll1_d4
> + - const: top_mux_aud_eng2
> + - const: top_apll2_d4
> + - const: top_i2s0_m_sel
> + - const: top_i2s1_m_sel
> + - const: top_i2s2_m_sel
> + - const: top_i2s3_m_sel
> + - const: top_i2s4_m_sel
> + - const: top_i2s5_m_sel
> + - const: top_i2s6_m_sel
> + - const: top_i2s7_m_sel
> + - const: top_i2s8_m_sel
> + - const: top_i2s9_m_sel
> + - const: top_apll12_div0
> + - const: top_apll12_div1
> + - const: top_apll12_div2
> + - const: top_apll12_div3
> + - const: top_apll12_div4
> + - const: top_apll12_divb
> + - const: top_apll12_div5
> + - const: top_apll12_div6
> + - const: top_apll12_div7
> + - const: top_apll12_div8
> + - const: top_apll12_div9
> + - const: top_mux_audio_h
> + - const: top_clk26m_clk
>
> required:
> - compatible
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