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Message-ID: <20250913064205.4152249-3-s-jain1@ti.com>
Date: Sat, 13 Sep 2025 12:12:05 +0530
From: Swamil Jain <s-jain1@...com>
To: <nm@...com>, <vigneshr@...com>, <kristo@...nel.org>, <robh@...nel.org>,
<krzk+dt@...nel.org>, <conor+dt@...nel.org>, <jyri.sarha@....fi>,
<tomi.valkeinen@...asonboard.com>, <maarten.lankhorst@...ux.intel.com>,
<mripard@...nel.org>, <tzimmermann@...e.de>, <airlied@...il.com>,
<simona@...ll.ch>, <aradhya.bhatia@...ux.dev>
CC: <h-shenoy@...com>, <devarsht@...com>, <praneeth@...com>, <u-kumar1@...com>,
<linux-arm-kernel@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<dri-devel@...ts.freedesktop.org>, <linux-kernel@...r.kernel.org>,
<s-jain1@...com>
Subject: [PATCH 2/2] arm64: dts: ti: k3-am625: Add OLDI support
From: Aradhya Bhatia <a-bhatia1@...com>
The AM625 SoC has 2 OLDI TXes under the DSS. Add their support.
Signed-off-by: Aradhya Bhatia <a-bhatia1@...com>
Signed-off-by: Swamil Jain <s-jain1@...com>
---
arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 47 ++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
index dcc71db8afd4..d240c157d819 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
@@ -793,6 +793,53 @@ dss: dss@...00000 {
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
+ oldi-transmitters {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ oldi0: oldi@0 {
+ reg = <0>;
+ clocks = <&k3_clks 186 0>;
+ clock-names = "serial";
+ ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ oldi0_port0: port@0 {
+ reg = <0>;
+ };
+
+ oldi0_port1: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ oldi1: oldi@1 {
+ reg = <1>;
+ clocks = <&k3_clks 186 0>;
+ clock-names = "serial";
+ ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ oldi1_port0: port@0 {
+ reg = <0>;
+ };
+
+ oldi1_port1: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+ };
+
dss_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
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