linux-kernel - Re: [PATCH 2/3] riscv: dts: thead: add ziccrse for th1520

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Message-ID: <CAAT7Ki_WD+X64oTPro=yn2de+Y_W9B2iDVE2cmRhV=TnQiUmPQ@mail.gmail.com>
Date: Sat, 13 Sep 2025 17:29:06 +0800
From: Han Gao <rabenda.cn@...il.com>
To: Conor Dooley <conor@...nel.org>
Cc: devicetree@...r.kernel.org, Drew Fustini <fustini@...nel.org>, 
	Guo Ren <guoren@...nel.org>, Fu Wei <wefu@...hat.com>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, 
	Albert Ou <aou@...s.berkeley.edu>, Alexandre Ghiti <alex@...ti.fr>, linux-riscv@...ts.infradead.org, 
	linux-kernel@...r.kernel.org, Han Gao <gaohan@...as.ac.cn>
Subject: Re: [PATCH 2/3] riscv: dts: thead: add ziccrse for th1520

On Sat, Sep 13, 2025 at 1:57 AM Conor Dooley <conor@...nel.org> wrote:
>
> On Fri, Sep 12, 2025 at 02:45:27AM +0800, Han Gao wrote:
> > th1520 support Ziccrse ISA extension [1].
> >
> > Link: https://lore.kernel.org/all/20241103145153.105097-12-alexghiti@rivosinc.com/ [1]
>
> I don't see what this link has to do with th1520 supporting the
> extension. The kernel supporting it has nothing to do with whether it
> should be in the dts or not. A useful link would substantiate your
> claim.

Existing rv64 hardware conforms to the rva20 profile.

Ziccrse is an additional extension required by the rva20 profile, so
th1520 has this extension.

Link: https://github.com/riscv/riscv-profiles/blob/main/src/profiles.adoc#511-rva20u64-mandatory-base
[1]

>
> > Signed-off-by: Han Gao <rabenda.cn@...il.com>
> > Signed-off-by: Han Gao <gaohan@...as.ac.cn>
>
> You only need to sign this off once.
>
> Cheers,
> Conor.
>
> > ---
> >  arch/riscv/boot/dts/thead/th1520.dtsi | 24 ++++++++++++++++--------
> >  1 file changed, 16 insertions(+), 8 deletions(-)
> >
> > diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> > index 59d1927764a6..7f07688aa964 100644
> > --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> > +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> > @@ -24,8 +24,10 @@ c910_0: cpu@0 {
> >                       device_type = "cpu";
> >                       riscv,isa = "rv64imafdc";
> >                       riscv,isa-base = "rv64i";
> > -                     riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> > -                                            "zifencei", "zihpm", "xtheadvector";
> > +                     riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > +                                            "ziccrse", "zicntr", "zicsr",
> > +                                            "zifencei", "zihpm",
> > +                                            "xtheadvector";
> >                       thead,vlenb = <16>;
> >                       reg = <0>;
> >                       i-cache-block-size = <64>;
> > @@ -49,8 +51,10 @@ c910_1: cpu@1 {
> >                       device_type = "cpu";
> >                       riscv,isa = "rv64imafdc";
> >                       riscv,isa-base = "rv64i";
> > -                     riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> > -                                            "zifencei", "zihpm", "xtheadvector";
> > +                     riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > +                                            "ziccrse", "zicntr", "zicsr",
> > +                                            "zifencei", "zihpm",
> > +                                            "xtheadvector";
> >                       thead,vlenb = <16>;
> >                       reg = <1>;
> >                       i-cache-block-size = <64>;
> > @@ -74,8 +78,10 @@ c910_2: cpu@2 {
> >                       device_type = "cpu";
> >                       riscv,isa = "rv64imafdc";
> >                       riscv,isa-base = "rv64i";
> > -                     riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> > -                                            "zifencei", "zihpm", "xtheadvector";
> > +                     riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > +                                            "ziccrse", "zicntr", "zicsr",
> > +                                            "zifencei", "zihpm",
> > +                                            "xtheadvector";
> >                       thead,vlenb = <16>;
> >                       reg = <2>;
> >                       i-cache-block-size = <64>;
> > @@ -99,8 +105,10 @@ c910_3: cpu@3 {
> >                       device_type = "cpu";
> >                       riscv,isa = "rv64imafdc";
> >                       riscv,isa-base = "rv64i";
> > -                     riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> > -                                            "zifencei", "zihpm", "xtheadvector";
> > +                     riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > +                                            "ziccrse", "zicntr", "zicsr",
> > +                                            "zifencei", "zihpm",
> > +                                            "xtheadvector";
> >                       thead,vlenb = <16>;
> >                       reg = <3>;
> >                       i-cache-block-size = <64>;
> > --
> > 2.47.3
> >