linux-kernel - Re: [PATCH v4 2/3] iio: adc: Support ROHM BD79112 ADC/GPIO

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Message-ID: <20250913132438.11d14416@jic23-huawei>
Date: Sat, 13 Sep 2025 13:24:38 +0100
From: Jonathan Cameron <jic23@...nel.org>
To: Matti Vaittinen <mazziesaccount@...il.com>
Cc: David Lechner <dlechner@...libre.com>, Nuno Sá
 <nuno.sa@...log.com>, Andy Shevchenko <andy@...nel.org>, Rob Herring
 <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Linus Walleij <linus.walleij@...aro.org>, Bartosz
 Golaszewski <brgl@...ev.pl>, linux-iio@...r.kernel.org,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-gpio@...r.kernel.org
Subject: Re: [PATCH v4 2/3] iio: adc: Support ROHM BD79112 ADC/GPIO

On Thu, 11 Sep 2025 08:13:03 +0300
Matti Vaittinen <mazziesaccount@...il.com> wrote:

> Morning Jonathan,
> 
> On 10/09/2025 20:46, Jonathan Cameron wrote:
> > On Wed, 10 Sep 2025 14:24:35 +0300
> > Matti Vaittinen <mazziesaccount@...il.com> wrote:
> >   
> >> The ROHM BD79112 is an ADC/GPIO with 32 channels. The channel inputs can
> >> be used as ADC or GPIO. Using the GPIOs as IRQ sources isn't supported.
> >>
> >> The ADC is 12-bit, supporting input voltages up to 5.7V, and separate I/O
> >> voltage supply. Maximum SPI clock rate is 20 MHz (10 MHz with
> >> daisy-chain configuration) and maximum sampling rate is 1MSPS.
> >>
> >> The IC does also support CRC but it is not implemented in the driver.
> >>
> >> Signed-off-by: Matti Vaittinen <mazziesaccount@...il.com>  
> > 
> > Hi Matti,
> > 
> > A few trivial things that I'll tidy up if nothing else comes up (I might not
> > bother given how trivial they are!)  
> 
> Thanks again!
> 
> > Also one question. I couldn't immediately follow why any random register
> > read is sanity checking if an ADC pin is configured as GPIO.
> >   
> 
> Ah. Valid question! I see my comment below is partially wrong.
> 
> 
> >> +/*
> >> + * Read transaction consists of two 16-bit sequences separated by CSB.
> >> + * For register read, 'IOSET' bit must be set. For ADC read, IOSET is cleared
> >> + * and ADDR equals the channel number (0 ... 31).
> >> + *
> >> + * First 16-bit sequence, MOSI as below, MISO data ignored:
> >> + * - SCK: | 1 | 2 |   3   |    4   | 5 .. 8 | 9 .. 16 |
> >> + * - MOSI:| 0 | 0 | IOSET | RW (1) |  ADDR  |  8'b0   |
> >> + *
> >> + * CSB released and re-acquired between these sequences
> >> + *
> >> + * Second 16-bit sequence, MISO as below, MOSI data ignored:
> >> + *   For Register read data is 8 bits:
> >> + *   - SCK: | 1 .. 8 |   9 .. 16   |
> >> + *   - MISO:|  8'b0  | 8-bit data  |
> >> + *
> >> + *   For ADC read data is 12 bits:
> >> + *   - SCK: | 1 .. 4 |   4 .. 16   |
> >> + *   - MISO:|  4'b0  | 12-bit data |  
> 
> This is not 100% true. I overlooked the ADC read "status flag" when 
> adding this comment for the ADC data reading.
> 
> This should be:
> 
>   *   For ADC, read data is 12 bits prepended with a status flag:
>   *   - SCK: | 1 |      2      | 3  4 |   4 .. 16   |
>   *   - MISO:| 0 | STATUS_FLAG | 2'b0 | 12-bit data |
> 
> The 'STATUS_FLAG' is set if the input pin is configured as a GPIO.

That's good additional info, but I'm still struggling on why
we are effectively providing a 'debug' check in ever register
read. My assumption is that it should never fire unless you have
a driver bug?  

Jonathan