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Message-Id: <20250915-msm8960-reorder-v1-1-84cadcd7c6e3@smankusors.com>
Date: Sun, 14 Sep 2025 18:34:43 +0000 (UTC)
From: Antony Kurniawan Soemardi <linux@...nkusors.com>
To: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Linus Walleij <linus.walleij@...aro.org>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
linux-gpio@...r.kernel.org, David Heidelberg <david@...t.cz>,
Max Shevchenko <wctrl@...ton.me>, Rudraksha Gupta <guptarud@...il.com>,
Shinjo Park <peremen@...il.com>,
Antony Kurniawan Soemardi <linux@...nkusors.com>
Subject: [PATCH 1/6] ARM: dts: qcom: msm8960: reorder nodes and properties
Reorder the nodes in qcom-msm8960.dtsi by unit address and sort
properties, as recommended in the Devicetree style guide. This is a
cosmetic change only, with no functional impact.
Tested-by: Rudraksha Gupta <guptarud@...il.com>
Tested-by: Shinjo Park <peremen@...il.com>
Signed-off-by: Antony Kurniawan Soemardi <linux@...nkusors.com>
---
arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 524 ++++++++++++++++---------------
1 file changed, 267 insertions(+), 257 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
index 532f16458756101b37954b5db92abec552bbc8db..9a0c87fd6d4752f7ef3d91f480c48efc55a08e74 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
@@ -15,6 +15,35 @@ / {
compatible = "qcom,msm8960";
interrupt-parent = <&intc>;
+ clocks {
+ cxo_board: cxo_board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ clock-output-names = "cxo_board";
+ };
+
+ pxo_board: pxo_board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ clock-output-names = "pxo_board";
+ };
+
+ sleep_clk: sleep_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "sleep_clk";
+ };
+ };
+
+ cpu-pmu {
+ compatible = "qcom,krait-pmu";
+ interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ qcom,no-pc-write;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -22,9 +51,9 @@ cpus {
cpu@0 {
compatible = "qcom,krait";
+ reg = <0>;
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
- reg = <0>;
next-level-cache = <&l2>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
@@ -32,9 +61,9 @@ cpu@0 {
cpu@1 {
compatible = "qcom,krait";
+ reg = <1>;
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
- reg = <1>;
next-level-cache = <&l2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
@@ -52,111 +81,27 @@ memory@...00000 {
reg = <0x80000000 0>;
};
- thermal-zones {
- cpu0-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsens 0>;
-
- trips {
- cpu_alert0: trip0 {
- temperature = <60000>;
- hysteresis = <10000>;
- type = "passive";
- };
-
- cpu_crit0: trip1 {
- temperature = <95000>;
- hysteresis = <10000>;
- type = "critical";
- };
- };
- };
-
- cpu1-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsens 1>;
-
- trips {
- cpu_alert1: trip0 {
- temperature = <60000>;
- hysteresis = <10000>;
- type = "passive";
- };
-
- cpu_crit1: trip1 {
- temperature = <95000>;
- hysteresis = <10000>;
- type = "critical";
- };
- };
- };
- };
-
- cpu-pmu {
- compatible = "qcom,krait-pmu";
- interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
- qcom,no-pc-write;
- };
-
- clocks {
- cxo_board: cxo_board {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <19200000>;
- clock-output-names = "cxo_board";
- };
-
- pxo_board: pxo_board {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <27000000>;
- clock-output-names = "pxo_board";
- };
-
- sleep_clk: sleep_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "sleep_clk";
- };
- };
-
- /* Temporary fixed regulator */
- vsdcc_fixed: vsdcc-regulator {
- compatible = "regulator-fixed";
- regulator-name = "SDCC Power";
- regulator-min-microvolt = <2700000>;
- regulator-max-microvolt = <2700000>;
- regulator-always-on;
- };
-
soc: soc {
+ compatible = "simple-bus";
+ ranges;
#address-cells = <1>;
#size-cells = <1>;
- ranges;
- compatible = "simple-bus";
- intc: interrupt-controller@...0000 {
- compatible = "qcom,msm-qgic2";
- interrupt-controller;
- #interrupt-cells = <3>;
- reg = <0x02000000 0x1000>,
- <0x02002000 0x1000>;
+ rpm: rpm@...000 {
+ compatible = "qcom,rpm-msm8960";
+ reg = <0x108000 0x1000>;
+ qcom,ipc = <&l2cc 0x8 2>;
+
+ interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ack", "err", "wakeup";
};
- timer@...a000 {
- compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer",
- "qcom,msm-timer";
- interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
- <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
- <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
- reg = <0x0200a000 0x100>;
- clock-frequency = <27000000>;
- clocks = <&sleep_clk>;
- clock-names = "sleep";
- cpu-offset = <0x80000>;
+ ssbi: ssbi@...000 {
+ compatible = "qcom,ssbi";
+ reg = <0x500000 0x1000>;
+ qcom,controller-type = "pmic-arbiter";
};
qfprom: efuse@...000 {
@@ -176,20 +121,20 @@ tsens_backup: backup-calib@414 {
msmgpio: pinctrl@...000 {
compatible = "qcom,msm8960-pinctrl";
+ reg = <0x800000 0x4000>;
gpio-controller;
gpio-ranges = <&msmgpio 0 0 152>;
#gpio-cells = <2>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
- reg = <0x800000 0x4000>;
};
gcc: clock-controller@...000 {
compatible = "qcom,gcc-msm8960", "syscon";
+ reg = <0x900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
- reg = <0x900000 0x4000>;
clocks = <&cxo_board>,
<&pxo_board>,
<&lcc PLL4>;
@@ -208,49 +153,25 @@ tsens: thermal-sensor {
};
};
- lcc: clock-controller@...00000 {
- compatible = "qcom,lcc-msm8960";
- reg = <0x28000000 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- clocks = <&pxo_board>,
- <&gcc PLL4_VOTE>,
- <0>,
- <0>, <0>,
- <0>, <0>,
- <0>;
- clock-names = "pxo",
- "pll4_vote",
- "mi2s_codec_clk",
- "codec_i2s_mic_codec_clk",
- "spare_i2s_mic_codec_clk",
- "codec_i2s_spkr_codec_clk",
- "spare_i2s_spkr_codec_clk",
- "pcm_codec_clk";
+ intc: interrupt-controller@...0000 {
+ compatible = "qcom,msm-qgic2";
+ reg = <0x02000000 0x1000>,
+ <0x02002000 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
};
- clock-controller@...0000 {
- compatible = "qcom,mmcc-msm8960";
- reg = <0x4000000 0x1000>;
- #clock-cells = <1>;
- #power-domain-cells = <1>;
- #reset-cells = <1>;
- clocks = <&pxo_board>,
- <&gcc PLL3>,
- <&gcc PLL8_VOTE>,
- <0>,
- <0>,
- <0>,
- <0>,
- <0>;
- clock-names = "pxo",
- "pll3",
- "pll8_vote",
- "dsi1pll",
- "dsi1pllbyte",
- "dsi2pll",
- "dsi2pllbyte",
- "hdmipll";
+ timer@...a000 {
+ compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer",
+ "qcom,msm-timer";
+ reg = <0x0200a000 0x100>;
+ interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
+ clock-frequency = <27000000>;
+ clocks = <&sleep_clk>;
+ clock-names = "sleep";
+ cpu-offset = <0x80000>;
};
l2cc: clock-controller@...1000 {
@@ -261,17 +182,6 @@ l2cc: clock-controller@...1000 {
#clock-cells = <0>;
};
- rpm: rpm@...000 {
- compatible = "qcom,rpm-msm8960";
- reg = <0x108000 0x1000>;
- qcom,ipc = <&l2cc 0x8 2>;
-
- interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "ack", "err", "wakeup";
- };
-
acc0: clock-controller@...8000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
@@ -281,15 +191,6 @@ acc0: clock-controller@...8000 {
#clock-cells = <0>;
};
- acc1: clock-controller@...8000 {
- compatible = "qcom,kpss-acc-v1";
- reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
- clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
- clock-names = "pll8_vote", "pxo";
- clock-output-names = "acpu1_aux";
- #clock-cells = <0>;
- };
-
saw0: power-manager@...9000 {
compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
@@ -300,6 +201,15 @@ saw0_vreg: regulator {
};
};
+ acc1: clock-controller@...8000 {
+ compatible = "qcom,kpss-acc-v1";
+ reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+ clock-names = "pll8_vote", "pxo";
+ clock-output-names = "acpu1_aux";
+ #clock-cells = <0>;
+ };
+
saw1: power-manager@...9000 {
compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
@@ -310,72 +220,34 @@ saw1_vreg: regulator {
};
};
- gsbi5: gsbi@...00000 {
- compatible = "qcom,gsbi-v1.0.0";
- cell-index = <5>;
- reg = <0x16400000 0x100>;
- clocks = <&gcc GSBI5_H_CLK>;
- clock-names = "iface";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- syscon-tcsr = <&tcsr>;
- status = "disabled";
-
- gsbi5_serial: serial@...40000 {
- compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
- reg = <0x16440000 0x1000>,
- <0x16400000 0x1000>;
- interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
- clock-names = "core", "iface";
- status = "disabled";
- };
- };
-
- gsbi8: gsbi@...00000 {
- compatible = "qcom,gsbi-v1.0.0";
- cell-index = <8>;
- reg = <0x1a000000 0x100>;
- clocks = <&gcc GSBI8_H_CLK>;
- clock-names = "iface";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- syscon-tcsr = <&tcsr>;
- status = "disabled";
-
- gsbi8_serial: serial@...40000 {
- compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
- reg = <0x1a040000 0x1000>,
- <0x1a000000 0x1000>;
- interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GSBI8_UART_CLK>, <&gcc GSBI8_H_CLK>;
- clock-names = "core", "iface";
- status = "disabled";
- };
- };
-
- ssbi: ssbi@...000 {
- compatible = "qcom,ssbi";
- reg = <0x500000 0x1000>;
- qcom,controller-type = "pmic-arbiter";
- };
-
- rng@...00000 {
- compatible = "qcom,prng";
- reg = <0x1a500000 0x200>;
- clocks = <&gcc PRNG_CLK>;
- clock-names = "core";
+ clock-controller@...0000 {
+ compatible = "qcom,mmcc-msm8960";
+ reg = <0x4000000 0x1000>;
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+ clocks = <&pxo_board>,
+ <&gcc PLL3>,
+ <&gcc PLL8_VOTE>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+ clock-names = "pxo",
+ "pll3",
+ "pll8_vote",
+ "dsi1pll",
+ "dsi1pllbyte",
+ "dsi2pll",
+ "dsi2pllbyte",
+ "hdmipll";
};
sdcc3: mmc@...80000 {
compatible = "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x00051180>;
- status = "disabled";
reg = <0x12180000 0x2000>;
+ arm,primecell-periphid = <0x00051180>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
clock-names = "mclk", "apb_pclk";
@@ -387,6 +259,8 @@ sdcc3: mmc@...80000 {
vmmc-supply = <&vsdcc_fixed>;
dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
dma-names = "tx", "rx";
+
+ status = "disabled";
};
sdcc3bam: dma-controller@...82000 {
@@ -400,10 +274,9 @@ sdcc3bam: dma-controller@...82000 {
};
sdcc1: mmc@...00000 {
- status = "disabled";
compatible = "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x00051180>;
reg = <0x12400000 0x2000>;
+ arm,primecell-periphid = <0x00051180>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
clock-names = "mclk", "apb_pclk";
@@ -415,6 +288,8 @@ sdcc1: mmc@...00000 {
vmmc-supply = <&vsdcc_fixed>;
dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
dma-names = "tx", "rx";
+
+ status = "disabled";
};
sdcc1bam: dma-controller@...02000 {
@@ -427,36 +302,6 @@ sdcc1bam: dma-controller@...02000 {
qcom,ee = <0>;
};
- tcsr: syscon@...00000 {
- compatible = "qcom,tcsr-msm8960", "syscon";
- reg = <0x1a400000 0x100>;
- };
-
- gsbi1: gsbi@...00000 {
- compatible = "qcom,gsbi-v1.0.0";
- cell-index = <1>;
- reg = <0x16000000 0x100>;
- clocks = <&gcc GSBI1_H_CLK>;
- clock-names = "iface";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- status = "disabled";
-
- gsbi1_spi: spi@...80000 {
- compatible = "qcom,spi-qup-v1.1.1";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x16080000 0x1000>;
- interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
- cs-gpios = <&msmgpio 8 0>;
-
- clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
- clock-names = "core", "iface";
- status = "disabled";
- };
- };
-
usb1: usb@...00000 {
compatible = "qcom,ci-hdrc";
reg = <0x12500000 0x200>,
@@ -473,6 +318,7 @@ usb1: usb@...00000 {
phys = <&usb_hs1_phy>;
phy-names = "usb-phy";
#reset-cells = <1>;
+
status = "disabled";
ulpi {
@@ -488,6 +334,32 @@ usb_hs1_phy: phy {
};
};
+ gsbi1: gsbi@...00000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ reg = <0x16000000 0x100>;
+ ranges;
+ cell-index = <1>;
+ clocks = <&gcc GSBI1_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ status = "disabled";
+
+ gsbi1_spi: spi@...80000 {
+ compatible = "qcom,spi-qup-v1.1.1";
+ reg = <0x16080000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ cs-gpios = <&msmgpio 8 0>;
+ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
+ clock-names = "core", "iface";
+
+ status = "disabled";
+ };
+ };
+
gsbi3: gsbi@...00000 {
compatible = "qcom,gsbi-v1.0.0";
reg = <0x16200000 0x100>;
@@ -497,6 +369,7 @@ gsbi3: gsbi@...00000 {
clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
+
status = "disabled";
gsbi3_i2c: i2c@...80000 {
@@ -511,9 +384,146 @@ gsbi3_i2c: i2c@...80000 {
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+
+ gsbi5: gsbi@...00000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ reg = <0x16400000 0x100>;
+ ranges;
+ cell-index = <5>;
+ clocks = <&gcc GSBI5_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ syscon-tcsr = <&tcsr>;
+
+ status = "disabled";
+
+ gsbi5_serial: serial@...40000 {
+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+ reg = <0x16440000 0x1000>,
+ <0x16400000 0x1000>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
+ clock-names = "core", "iface";
+
+ status = "disabled";
+ };
+ };
+
+ gsbi8: gsbi@...00000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ reg = <0x1a000000 0x100>;
+ ranges;
+ cell-index = <8>;
+ clocks = <&gcc GSBI8_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ syscon-tcsr = <&tcsr>;
+
+ status = "disabled";
+
+ gsbi8_serial: serial@...40000 {
+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+ reg = <0x1a040000 0x1000>,
+ <0x1a000000 0x1000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI8_UART_CLK>, <&gcc GSBI8_H_CLK>;
+ clock-names = "core", "iface";
+
status = "disabled";
};
};
+
+ tcsr: syscon@...00000 {
+ compatible = "qcom,tcsr-msm8960", "syscon";
+ reg = <0x1a400000 0x100>;
+ };
+
+ rng@...00000 {
+ compatible = "qcom,prng";
+ reg = <0x1a500000 0x200>;
+ clocks = <&gcc PRNG_CLK>;
+ clock-names = "core";
+ };
+
+ lcc: clock-controller@...00000 {
+ compatible = "qcom,lcc-msm8960";
+ reg = <0x28000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ clocks = <&pxo_board>,
+ <&gcc PLL4_VOTE>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+ clock-names = "pxo",
+ "pll4_vote",
+ "mi2s_codec_clk",
+ "codec_i2s_mic_codec_clk",
+ "spare_i2s_mic_codec_clk",
+ "codec_i2s_spkr_codec_clk",
+ "spare_i2s_spkr_codec_clk",
+ "pcm_codec_clk";
+ };
+ };
+
+ thermal-zones {
+ cpu0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsens 0>;
+
+ trips {
+ cpu_alert0: trip0 {
+ temperature = <60000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+
+ cpu_crit0: trip1 {
+ temperature = <95000>;
+ hysteresis = <10000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsens 1>;
+
+ trips {
+ cpu_alert1: trip0 {
+ temperature = <60000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+
+ cpu_crit1: trip1 {
+ temperature = <95000>;
+ hysteresis = <10000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
+ /* Temporary fixed regulator */
+ vsdcc_fixed: vsdcc-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "SDCC Power";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ regulator-always-on;
};
};
#include "qcom-msm8960-pins.dtsi"
--
2.34.1
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