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Message-ID: <20250915-exynos9610-clocks-v1-1-3f615022b178@chimac.ro>
Date: Sun, 14 Sep 2025 21:19:19 +0000
From: Alexandru Chimac <alex@...mac.ro>
To: Krzysztof Kozlowski <krzk@...nel.org>, Sylwester Nawrocki <s.nawrocki@...sung.com>, Chanwoo Choi <cw00.choi@...sung.com>, Alim Akhtar <alim.akhtar@...sung.com>, Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Alexandru Chimac <alexchimac@...tonmail.com>, Krzysztof Kozlowski <krzk+dt@...nel.org>
Cc: linux-samsung-soc@...r.kernel.org, linux-clk@...r.kernel.org, devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, Alexandru Chimac <alex@...mac.ro>
Subject: [PATCH 1/8] dt-bindings: clock: samsung: Add Exynos9610 CMU bindings
This clock management unit has a topmost block (CMU_TOP)
that generates top clocks for other blocks, alongside 20
other blocks, out of which 11 are currently implemented.
Signed-off-by: Alexandru Chimac <alex@...mac.ro>
---
.../bindings/clock/samsung,exynos9610-clock.yaml | 344 ++++++++++
include/dt-bindings/clock/samsung,exynos9610.h | 720 +++++++++++++++++++++
2 files changed, 1064 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos9610-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos9610-clock.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..f3b7bc49a6ab18c5dd3c54d1f5fcdb7a67d15668
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos9610-clock.yaml
@@ -0,0 +1,344 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynos9610-clock.yaml
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos9610 SoC clock controller
+
+maintainers:
+ - Alexandru Chimac <alexchimac@...tonmail.com>
+ - Chanwoo Choi <cw00.choi@...sung.com>
+ - Krzysztof Kozlowski <krzk@...nel.org>
+
+description: |
+ Exynos9610 clock controller is comprised of several CMU units, generating
+ clocks for different domains. Those CMU units are modeled as separate device
+ tree nodes, and might depend on each other. Root clocks in that clock tree are
+ three external clocks:: OSCCLK (26MHz), DLL_DCO (360MHz), OSCCLK_RCO (CMGP, 30MHz).
+ The external OSCCLK must be defined as fixed-rate clock in the device tree.
+
+ CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs
+ and dividers; all other clocks of function blocks (other CMUs) are usually derived
+ from CMU_TOP.
+
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All clocks available for usage
+ in clock consumer nodes are defined as preprocessor macros
+ in 'include/dt-bindings/clock/samsung,exynos9610.h'.
+
+properties:
+ compatible:
+ enum:
+ - samsung,exynos9610-cmu-top
+ - samsung,exynos9610-cmu-apm
+ - samsung,exynos9610-cmu-cam
+ - samsung,exynos9610-cmu-cmgp
+ - samsung,exynos9610-cmu-core
+ - samsung,exynos9610-cmu-cpucl0
+ - samsung,exynos9610-cmu-cpucl1
+ - samsung,exynos9610-cmu-dispaud
+ - samsung,exynos9610-cmu-fsys
+ - samsung,exynos9610-cmu-g2d
+ - samsung,exynos9610-cmu-g3d
+ - samsung,exynos9610-cmu-peri
+
+ clocks:
+ minItems: 1
+ maxItems: 7
+
+ clock-names:
+ minItems: 1
+ maxItems: 7
+
+ "#clock-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos9610-cmu-top
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26MHz)
+
+ clock-names:
+ items:
+ - const: oscclk
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos9610-cmu-apm
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26MHz)
+ - description: External reference clock (360Mhz)
+ - description: CMU_APM bus clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dll_dco
+ - const: dout_cmu_apm_bus
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos9610-cmu-cam
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26MHz)
+ - description: CMU_CAM bus clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_cmu_cam_bus
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos9610-cmu-cmgp
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26MHz)
+ - description: External reference clock (30MHz)
+ - description: CMU_CMGP bus clock (from CMU_APM)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: oscclk_rco
+ - const: gout_cmu_cmgp_bus
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos9610-cmu-core
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26MHz)
+ - description: CMU_CORE bus clock (from CMU_TOP)
+ - description: CMU_CORE CCI clock (from CMU_TOP)
+ - description: CMU_CORE G3D clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: gout_cmu_core_bus
+ - const: gout_cmu_core_cci
+ - const: gout_cmu_core_g3d
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos9610-cmu-cpucl0
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26MHz)
+ - description: CMU_CPUCL0 debug clock (from CMU_TOP)
+ - description: CMU_CPUCL0 switch clock (from CMU_TOP)
+ - description: HPM clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_cmu_cpucl0_dbg
+ - const: dout_cmu_cpucl0_switch
+ - const: dout_cmu_hpm
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos9610-cmu-cpucl1
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26MHz)
+ - description: CMU_CPUCL1 switch clock (from CMU_TOP)
+ - description: HPM clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_cmu_cpucl1_switch
+ - const: dout_cmu_hpm
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos9610-cmu-dispaud
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26MHz)
+ - description: External reference clock (10Mhz)
+ - description: External reference clock (100Mhz)
+ - description: External reference clock (60Mhz)
+ - description: CMU_DISPAUD audio clock (from CMU_TOP)
+ - description: CMU_DISPAUD CPU clock (from CMU_TOP)
+ - description: CMU_DISPAUD display clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: ioclk_audiocdclk0
+ - const: ioclk_audiocdclk1
+ - const: tick_usb
+ - const: dout_cmu_dispaud_aud
+ - const: dout_cmu_dispaud_cpu
+ - const: dout_cmu_dispaud_disp
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos9610-cmu-fsys
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26MHz)
+ - description: CMU_FSYS bus clock (from CMU_TOP)
+ - description: CMU_FSYS external MMC clock (from CMU_TOP)
+ - description: CMU_FSYS embedded MMC clock (from CMU_TOP)
+ - description: CMU_FSYS embedded UFS clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_cmu_fsys_bus
+ - const: dout_cmu_fsys_mmc_card
+ - const: dout_cmu_fsys_mmc_embd
+ - const: dout_cmu_fsys_ufs_embd
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos9610-cmu-g2d
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26MHz)
+ - description: CMU_G2D G2D clock (from CMU_TOP)
+ - description: CMU_G2D MSCL clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_cmu_g2d_g2d
+ - const: dout_cmu_g2d_mscl
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos9610-cmu-g3d
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26MHz)
+ - description: CMU_G3D switch clock (from CMU_TOP)
+ - description: HPM clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_cmu_g3d_switch
+ - const: dout_cmu_hpm
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos9610-cmu-peri
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26MHz)
+ - description: CMU_PERI bus clock (from CMU_TOP)
+ - description: CMU_PERI IP clock (from CMU_TOP)
+ - description: CMU_PERI UART clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_cmu_peri_bus
+ - const: dout_cmu_peri_ip
+ - const: dout_cmu_peri_uart
+
+required:
+ - compatible
+ - "#clock-cells"
+ - clocks
+ - clock-names
+ - reg
+
+additionalProperties: false
+
+examples:
+ # Clock controller node for CMU_FSYS
+ - |
+ #include <dt-bindings/clock/samsung,exynos9610.h>
+
+ cmu_fsys: clock-controller@...00000 {
+ compatible = "samsung,exynos9610-cmu-fsys";
+ reg = <0x13400000 0x8000>;
+ #clock-cells = <1>
+
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_CMU_FSYS_BUS>,
+ <&cmu_top CLK_DOUT_CMU_FSYS_MMC_CARD>,
+ <&cmu_top CLK_DOUT_CMU_FSYS_MMC_EMBD>,
+ <&cmu_top CLK_DOUT_CMU_FSYS_UFS_EMBD>,
+
+ clock-names = "oscclk",
+ "dout_cmu_fsys_bus",
+ "dout_cmu_fsys_mmc_card",
+ "dout_cmu_fsys_mmc_embd",
+ "dout_cmu_fsys_ufs_embd";
+ };
+...
diff --git a/include/dt-bindings/clock/samsung,exynos9610.h b/include/dt-bindings/clock/samsung,exynos9610.h
new file mode 100644
index 0000000000000000000000000000000000000000..047c35fd8bf133996aaa185f9c8e5457499e707e
--- /dev/null
+++ b/include/dt-bindings/clock/samsung,exynos9610.h
@@ -0,0 +1,720 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Device tree binding constants for Exynos9610 clocks
+ *
+ * Copyright (c) 2025, Alexandru Chimac <alex@...mac.ro>
+ */
+
+/* CMU_TOP PLLs */
+#define CLK_FOUT_SHARED0_PLL 1
+#define CLK_FOUT_SHARED1_PLL 2
+#define CLK_FOUT_MMC_PLL 3
+
+/* CMU_TOP muxes */
+#define CLK_MOUT_PLL_SHARED0 4
+#define CLK_MOUT_PLL_SHARED1 5
+#define CLK_MOUT_PLL_MMC 6
+#define CLK_MOUT_CMU_APM_BUS 7
+#define CLK_MOUT_CMU_CAM_BUS 8
+#define CLK_MOUT_CMU_CIS_CLK0 9
+#define CLK_MOUT_CMU_CIS_CLK1 10
+#define CLK_MOUT_CMU_CIS_CLK2 11
+#define CLK_MOUT_CMU_CIS_CLK3 12
+#define CLK_MOUT_CMU_CORE_BUS 13
+#define CLK_MOUT_CMU_CORE_CCI 14
+#define CLK_MOUT_CMU_CORE_G3D 15
+#define CLK_MOUT_CMU_CPUCL0_DBG 16
+#define CLK_MOUT_CMU_CPUCL0_SWITCH 17
+#define CLK_MOUT_CMU_CPUCL1_SWITCH 18
+#define CLK_MOUT_CMU_DISPAUD_AUD 19
+#define CLK_MOUT_CMU_DISPAUD_CPU 20
+#define CLK_MOUT_CMU_DISPAUD_DISP 21
+#define CLK_MOUT_CMU_FSYS_BUS 22
+#define CLK_MOUT_CMU_FSYS_MMC_CARD 23
+#define CLK_MOUT_CMU_FSYS_MMC_EMBD 24
+#define CLK_MOUT_CMU_FSYS_UFS_EMBD 25
+#define CLK_MOUT_CMU_G2D_G2D 26
+#define CLK_MOUT_CMU_G2D_MSCL 27
+#define CLK_MOUT_CMU_G3D_SWITCH 28
+#define CLK_MOUT_CMU_HPM 29
+#define CLK_MOUT_CMU_ISP_BUS 30
+#define CLK_MOUT_CMU_ISP_GDC 31
+#define CLK_MOUT_CMU_ISP_VRA 32
+#define CLK_MOUT_CMU_MFC_MFC 33
+#define CLK_MOUT_CMU_MFC_WFD 34
+#define CLK_MOUT_CMU_MIF_BUSP 35
+#define CLK_MOUT_CMU_MIF_SWITCH 36
+#define CLK_MOUT_CMU_PERI_BUS 37
+#define CLK_MOUT_CMU_PERI_IP 38
+#define CLK_MOUT_CMU_PERI_UART 39
+#define CLK_MOUT_CMU_USB_BUS 40
+#define CLK_MOUT_CMU_USB_DPGTC 41
+#define CLK_MOUT_CMU_USB_USB30DRD 42
+#define CLK_MOUT_CMU_VIPX1_BUS 43
+#define CLK_MOUT_CMU_VIPX2_BUS 44
+#define CLK_MOUT_CLK_CMU_CMUREF 45
+#define CLK_MOUT_CMU_CMUREF 46
+
+/* CMU_TOP dividers */
+#define CLK_DOUT_CMU_SHARED0_DIV2 47
+#define CLK_DOUT_CMU_SHARED0_DIV3 48
+#define CLK_DOUT_CMU_SHARED0_DIV4 49
+#define CLK_DOUT_CMU_SHARED1_DIV2 50
+#define CLK_DOUT_CMU_SHARED1_DIV3 51
+#define CLK_DOUT_CMU_SHARED1_DIV4 52
+#define CLK_DOUT_CMU_MMC_DIV2 53
+#define CLK_DOUT_AP2CP_SHARED0_PLL_CLK 54
+#define CLK_DOUT_AP2CP_SHARED1_PLL_CLK 55
+#define CLK_DOUT_CMU_APM_BUS 56
+#define CLK_DOUT_CMU_CAM_BUS 57
+#define CLK_DOUT_CMU_CIS_CLK0 58
+#define CLK_DOUT_CMU_CIS_CLK1 59
+#define CLK_DOUT_CMU_CIS_CLK2 60
+#define CLK_DOUT_CMU_CIS_CLK3 61
+#define CLK_DOUT_CMU_CORE_BUS 62
+#define CLK_DOUT_CMU_CORE_CCI 63
+#define CLK_DOUT_CMU_CORE_G3D 64
+#define CLK_DOUT_CMU_CPUCL0_DBG 65
+#define CLK_DOUT_CMU_CPUCL0_SWITCH 66
+#define CLK_DOUT_CMU_CPUCL1_SWITCH 67
+#define CLK_DOUT_CMU_DISPAUD_AUD 68
+#define CLK_DOUT_CMU_DISPAUD_CPU 69
+#define CLK_DOUT_CMU_DISPAUD_DISP 70
+#define CLK_DOUT_CMU_FSYS_BUS 71
+#define CLK_DOUT_CMU_FSYS_MMC_CARD 72
+#define CLK_DOUT_CMU_FSYS_MMC_EMBD 73
+#define CLK_DOUT_CMU_FSYS_UFS_EMBD 74
+#define CLK_DOUT_CMU_G2D_G2D 75
+#define CLK_DOUT_CMU_G2D_MSCL 76
+#define CLK_DOUT_CMU_G3D_SWITCH 77
+#define CLK_DOUT_CMU_HPM 78
+#define CLK_DOUT_CMU_ISP_BUS 79
+#define CLK_DOUT_CMU_ISP_GDC 80
+#define CLK_DOUT_CMU_ISP_VRA 81
+#define CLK_DOUT_CMU_MFD_MFC 82
+#define CLK_DOUT_CMU_MFD_WFD 83
+#define CLK_DOUT_CMU_MIF_BUSP 84
+#define CLK_DOUT_CMU_PERI_BUS 85
+#define CLK_DOUT_CMU_PERI_IP 86
+#define CLK_DOUT_CMU_PERI_UART 87
+#define CLK_DOUT_CMU_USB_BUS 88
+#define CLK_DOUT_CMU_USB_DPGTC 89
+#define CLK_DOUT_CMU_USB_USB30DRD 90
+#define CLK_DOUT_CMU_VIPX1_BUS 91
+#define CLK_DOUT_CMU_VIPX2_BUS 92
+#define CLK_DOUT_CLK_CMU_CMUREF 93
+#define CLK_DOUT_CMU_OTP 94
+
+/* CMU_TOP gates */
+#define CLK_GOUT_CMU_MIF_SWITCH 95
+#define CLK_GOUT_CLK_CMU_OTP_CLK 96
+#define CLK_GOUT_CMU_APM_BUS 97
+#define CLK_GOUT_CMU_CAM_BUS 98
+#define CLK_GOUT_CMU_CIS_CLK0 99
+#define CLK_GOUT_CMU_CIS_CLK1 100
+#define CLK_GOUT_CMU_CIS_CLK2 101
+#define CLK_GOUT_CMU_CIS_CLK3 102
+#define CLK_GOUT_CMU_CORE_BUS 103
+#define CLK_GOUT_CMU_CORE_CCI 104
+#define CLK_GOUT_CMU_CORE_G3D 105
+#define CLK_GOUT_CMU_CPUCL0_DBG 106
+#define CLK_GOUT_CMU_CPUCL0_SWITCH 107
+#define CLK_GOUT_CMU_CPUCL1_SWITCH 108
+#define CLK_GOUT_CMU_DISPAUD_AUD 109
+#define CLK_GOUT_CMU_DISPAUD_CPU 110
+#define CLK_GOUT_CMU_DISPAUD_DISP 111
+#define CLK_GOUT_CMU_FSYS_BUS 112
+#define CLK_GOUT_CMU_FSYS_MMC_CARD 113
+#define CLK_GOUT_CMU_FSYS_MMC_EMBD 114
+#define CLK_GOUT_CMU_FSYS_UFS_EMBD 115
+#define CLK_GOUT_CMU_G2D_G2D 116
+#define CLK_GOUT_CMU_G2D_MSCL 117
+#define CLK_GOUT_CMU_G3D_SWITCH 118
+#define CLK_GOUT_CMU_HPM 119
+#define CLK_GOUT_CMU_ISP_BUS 120
+#define CLK_GOUT_CMU_ISP_GDC 121
+#define CLK_GOUT_CMU_ISP_VRA 122
+#define CLK_GOUT_CMU_MFC_MFC 123
+#define CLK_GOUT_CMU_MFC_WFD 124
+#define CLK_GOUT_CMU_MIF_BUSP 125
+#define CLK_GOUT_CMU_MODEM_SHARED0 126
+#define CLK_GOUT_CMU_MODEM_SHARED1 127
+#define CLK_GOUT_CMU_PERI_BUS 128
+#define CLK_GOUT_CMU_PERI_IP 129
+#define CLK_GOUT_CMU_PERI_UART 130
+#define CLK_GOUT_CMU_USB_BUS 131
+#define CLK_GOUT_CMU_USB_DPGTC 132
+#define CLK_GOUT_CMU_USB_USB30DRD 133
+#define CLK_GOUT_CMU_VIPX1_BUS 134
+#define CLK_GOUT_CMU_VIPX2_BUS 135
+
+/* CMU_APM muxes */
+#define CLK_MOUT_PLL_APM_BUS_USER 1
+#define CLK_MOUT_PLL_DLL_USER 2
+#define CLK_MOUT_CMU_SHUB_BUS 3
+#define CLK_MOUT_CLK_APM_BUS 4
+
+/* CMU_APM dividers */
+#define CLK_DOUT_CMU_SHUB_BUS 5
+#define CLK_DOUT_CLK_APM_BUS 6
+
+/* CPU_APM gates */
+#define CLK_GOUT_CMU_CMGP_BUS 7
+#define CLK_GOUT_CLK_APM_CMU_PCLK 8
+#define CLK_GOUT_CLK_APM_OSCCLK_CLK 9
+#define CLK_GOUT_CLK_APM_OSCCLK_RCO_CLK 10
+#define CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 11
+#define CLK_GOUT_APM_APBIF_PMU_ALIVE_PCLK 12
+#define CLK_GOUT_APM_APBIF_RTC_ALIVE_PCLK 12
+#define CLK_GOUT_APM_APBIF_TOP_RTC_ALIVE_PCLK 13
+#define CLK_GOUT_APM_GREBEINTEGRATION_HCLK 14
+#define CLK_GOUT_APM_INTMEM_ACLK 15
+#define CLK_GOUT_APM_INTMEM_PCLK 16
+#define CLK_GOUT_APM_LHM_AXI_P_GNSS_CLK 17
+#define CLK_GOUT_APM_LHM_AXI_P_CLK 18
+#define CLK_GOUT_APM_LHM_AXI_P_MODEM_CLK 19
+#define CLK_GOUT_APM_LHM_AXI_P_SHUB_CLK 20
+#define CLK_GOUT_APM_LHM_AXI_P_WLBT_CLK 21
+#define CLK_GOUT_APM_LHS_AXI_D_CLK 22
+#define CLK_GOUT_APM_LHS_AXI_LP_SHUB_CLK 23
+#define CLK_GOUT_APM_MAILBOX_AP2CP_PCLK 24
+#define CLK_GOUT_APM_MAILBOX_AP2CP_S_PCLK 25
+#define CLK_GOUT_APM_MAILBOX_AP2GNSS_PCLK 26
+#define CLK_GOUT_APM_MAILBOX_AP2SHUB_PCLK 27
+#define CLK_GOUT_APM_MAILBOX_AP2WLBT_PCLK 28
+#define CLK_GOUT_APM_MAILBOX_APM2AP_PCLK 29
+#define CLK_GOUT_APM_MAILBOX_APM2CP_PCLK 30
+#define CLK_GOUT_APM_MAILBOX_APM2GNSS_PCLK 31
+#define CLK_GOUT_APM_MAILBOX_APM2SHUB_PCLK 32
+#define CLK_GOUT_APM_MAILBOX_APM2WLBT_PCLK 33
+#define CLK_GOUT_APM_MAILBOX_CP2GNSS_PCLK 34
+#define CLK_GOUT_APM_MAILBOX_CP2SHUB_PCLK 35
+#define CLK_GOUT_APM_MAILBOX_CP2WLBT_PCLK 36
+#define CLK_GOUT_APM_MAILBOX_SHUB2GNSS_PCLK 37
+#define CLK_GOUT_APM_MAILBOX_SHUB2WLBT_PCLK 38
+#define CLK_GOUT_APM_MAILBOX_WLBT2ABOX_PCLK 39
+#define CLK_GOUT_APM_MAILBOX_WLBT2GNSS_PCLK 40
+#define CLK_GOUT_APM_PEM_CLK 41
+#define CLK_GOUT_APM_PGEN_LITE_CLK 42
+#define CLK_GOUT_APM_PMU_INTR_GEN_PCLK 43
+#define CLK_GOUT_APM_BUS_CLK 44
+#define CLK_GOUT_APM_GREBE_CLK 45
+#define CLK_GOUT_APM_SPEEDY_PCLK 46
+#define CLK_GOUT_APM_SYSREG_PCLK 47
+#define CLK_GOUT_APM_WDT_PCLK 48
+#define CLK_GOUT_APM_XIU_DP_ACLK 49
+
+/* CMU_CAM muxes */
+#define CLK_MOUT_PLL_CAM_BUS_USER 1
+
+/* CMU_CAM dividers */
+#define CLK_DIV_CLK_CAM_BUSP 2
+
+/* CMU_CAM gates */
+#define CLK_GAT_CLK_CAM_CMU_PCLK 3
+#define CLK_GAT_CLK_CAM_OSCCLK_CLK 4
+#define CLK_GOUT_CAM_BUSD 5
+#define CLK_GOUT_CAM_BTM_ACLK 6
+#define CLK_GOUT_CAM_BTM_PCLK 7
+#define CLK_GOUT_CAM_LHS_ATB_CAMISP_CLK 8
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_3AA 9
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_CSIS0 10
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_CSIS1 11
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_CSIS2 12
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_CSIS3 13
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_RDMA 14
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS0 15
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS1 16
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS2 17
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS3 18
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_PAFSTAT_CORE 19
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_PPMU_CAM 20
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_DMA 21
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_SMMU_CAM 22
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_XIU_D_CAM 23
+#define CLK_GOUT_CAM_IS6P10P0_PCLK_PGEN_LITE_CAM0 24
+#define CLK_GOUT_CAM_IS6P10P0_PCLK_PGEN_LITE_CAM1 25
+#define CLK_GOUT_CAM_IS6P10P0_PCLK_PPMU_CAM 26
+#define CLK_GOUT_CAM_LHM_AXI_P_CLK 27
+#define CLK_GOUT_CAM_LHS_ACEL_D_CLK 28
+#define CLK_GOUT_CAM_BUSD_CLK 29
+#define CLK_GOUT_CAM_BUSP_CLK 30
+#define CLK_GOUT_CAM_SYSREG_PCLK 31
+
+/* CMU_CMGP muxes */
+#define CLK_MOUT_CLK_CMGP_ADC 0
+#define CLK_MOUT_CLK_CMGP_I2C 1
+#define CLK_MOUT_CLK_CMGP_USI00 2
+#define CLK_MOUT_CLK_CMGP_USI01 3
+#define CLK_MOUT_CLK_CMGP_USI02 4
+#define CLK_MOUT_CLK_CMGP_USI03 5
+#define CLK_MOUT_CLK_CMGP_USI04 6
+
+/* CMU_CMGP dividers */
+#define CLK_DOUT_CLK_CMGP_ADC 0
+#define CLK_DOUT_CLK_CMGP_I2C 1
+#define CLK_DOUT_CLK_CMGP_USI00 2
+#define CLK_DOUT_CLK_CMGP_USI01 3
+#define CLK_DOUT_CLK_CMGP_USI02 4
+#define CLK_DOUT_CLK_CMGP_USI03 5
+#define CLK_DOUT_CLK_CMGP_USI04 6
+
+/* CMU_CMGP gates */
+#define CLK_GOUT_CMGP_CMU_PCLK 7
+#define CLK_GOUT_CLK_CMGP_OSCCLK_RCO_CLK 8
+#define CLK_GOUT_CMGP_ADC_PCLK_S0 9
+#define CLK_GOUT_CMGP_ADC_PCLK_S1 10
+#define CLK_GOUT_CMGP_GPIO_PCLK 11
+#define CLK_GOUT_CMGP_I2C_CMGP00_IPCLK 12
+#define CLK_GOUT_CMGP_I2C_CMGP00_PCLK 13
+#define CLK_GOUT_CMGP_I2C_CMGP01_IPCLK 14
+#define CLK_GOUT_CMGP_I2C_CMGP01_PCLK 15
+#define CLK_GOUT_CMGP_I2C_CMGP02_IPCLK 16
+#define CLK_GOUT_CMGP_I2C_CMGP02_PCLK 17
+#define CLK_GOUT_CMGP_I2C_CMGP03_IPCLK 18
+#define CLK_GOUT_CMGP_I2C_CMGP03_PCLK 19
+#define CLK_GOUT_CMGP_I2C_CMGP04_IPCLK 20
+#define CLK_GOUT_CMGP_I2C_CMGP04_PCLK 21
+#define CLK_GOUT_CMGP_BUS_CLK 22
+#define CLK_GOUT_CMGP_I2C_CLK 23
+#define CLK_GOUT_CMGP_USI00_CLK 24
+#define CLK_GOUT_CMGP_USI01_CLK 25
+#define CLK_GOUT_CMGP_USI02_CLK 26
+#define CLK_GOUT_CMGP_USI03_CLK 27
+#define CLK_GOUT_CMGP_USI04_CLK 28
+#define CLK_GOUT_CMGP_SYSREG_CMGP2CP_PCLK 29
+#define CLK_GOUT_CMGP_SYSREG_CMGP2GNSS_PCLK 30
+#define CLK_GOUT_CMGP_SYSREG_CMGP2PMU_AP_PCLK 31
+#define CLK_GOUT_CMGP_SYSREG_CMGP2PMU_SHUB_PCLK 32
+#define CLK_GOUT_CMGP_SYSREG_CMGP2SHUB_PCLK 33
+#define CLK_GOUT_CMGP_SYSREG_CMGP2WLBT_PCLK 34
+#define CLK_GOUT_CMGP_SYSREG_PCLK 35
+#define CLK_GOUT_CMGP_USI_CMGP00_IPCLK 36
+#define CLK_GOUT_CMGP_USI_CMGP00_PCLK 37
+#define CLK_GOUT_CMGP_USI_CMGP01_IPCLK 38
+#define CLK_GOUT_CMGP_USI_CMGP01_PCLK 39
+#define CLK_GOUT_CMGP_USI_CMGP02_IPCLK 40
+#define CLK_GOUT_CMGP_USI_CMGP02_PCLK 41
+#define CLK_GOUT_CMGP_USI_CMGP03_IPCLK 42
+#define CLK_GOUT_CMGP_USI_CMGP03_PCLK 43
+#define CLK_GOUT_CMGP_USI_CMGP04_IPCLK 44
+#define CLK_GOUT_CMGP_USI_CMGP04_PCLK 45
+
+/* CMU_CORE muxes */
+#define CLK_MOUT_PLL_CORE_BUS_USER 1
+#define CLK_MOUT_PLL_CORE_CCI_USER 2
+#define CLK_MOUT_PLL_CORE_G3D_USER 3
+#define CLK_MOUT_CLK_CORE_GIC 4
+
+/* CMU_CORE dividers */
+#define CLK_DOUT_CLK_CORE_BUSP 5
+
+/* CMU_CORE gates */
+#define CLK_GOUT_CLK_CORE_CMU_PCLK 6
+#define CLK_GOUT_CORE_AD_APB_CCI_550_PCLKM 7
+#define CLK_GOUT_CORE_AD_APB_DIT_PCLKM 8
+#define CLK_GOUT_CORE_AD_APB_PDMA0_PCLKM 9
+#define CLK_GOUT_CORE_AD_APB_PGEN_PDMA_PCLKM 10
+#define CLK_GOUT_CORE_AD_APB_PPFW_MEM0_PCLKM 11
+#define CLK_GOUT_CORE_AD_APB_PPFW_MEM1_PCLKM 12
+#define CLK_GOUT_CORE_AD_APB_PPFW_PERI_PCLKM 13
+#define CLK_GOUT_CORE_AD_APB_SPDMA_PCLKM 14
+#define CLK_GOUT_CORE_AD_AXI_GIC_ACLKM 15
+#define CLK_GOUT_CORE_ASYNCSFR_WR_DMC0_PCLK 16
+#define CLK_GOUT_CORE_ASYNCSFR_WR_DMC1_PCLK 17
+#define CLK_GOUT_CORE_AXI_US_A40_64TO128_DIT_ACLK 18
+#define CLK_GOUT_CORE_BAAW_P_GNSS_PCLK 19
+#define CLK_GOUT_CORE_BAAW_P_MODEM_PCLK 20
+#define CLK_GOUT_CORE_BAAW_P_SHUB_PCLK 21
+#define CLK_GOUT_CORE_BAAW_P_WLBT_PCLK 22
+#define CLK_GOUT_CORE_CCI_550_ACLK 23
+#define CLK_GOUT_CORE_DIT_ICLKL2A 24
+#define CLK_GOUT_CORE_GIC400_AIHWACG_CLK 25
+#define CLK_GOUT_CORE_LHM_ACEL_D0_ISP_CLK 26
+#define CLK_GOUT_CORE_LHM_ACEL_D0_MFC_CLK 27
+#define CLK_GOUT_CORE_LHM_ACEL_D1_ISP_CLK 28
+#define CLK_GOUT_CORE_LHM_ACEL_D1_MFC_CLK 29
+#define CLK_GOUT_CORE_LHM_ACEL_D_CAM_CLK 30
+#define CLK_GOUT_CORE_LHM_ACEL_D_DPU_CLK 31
+#define CLK_GOUT_CORE_LHM_ACEL_D_FSYS_CLK 32
+#define CLK_GOUT_CORE_LHM_ACEL_D_G2D_CLK 33
+#define CLK_GOUT_CORE_LHM_ACEL_D_USB_CLK 34
+#define CLK_GOUT_CORE_LHM_ACEL_D_VIPX1_CLK 35
+#define CLK_GOUT_CORE_LHM_ACEL_D_VIPX2_CLK 36
+#define CLK_GOUT_CORE_LHM_ACE_D_CPUCL0_CLK 37
+#define CLK_GOUT_CORE_LHM_ACE_D_CPUCL1_CLK 38
+#define CLK_GOUT_CORE_LHM_AXI_D0_MODEM_CLK 39
+#define CLK_GOUT_CORE_LHM_AXI_D1_MODEM_CLK 40
+#define CLK_GOUT_CORE_LHM_AXI_D_ABOX_CLK 41
+#define CLK_GOUT_CORE_LHM_AXI_D_APM_CLK 42
+#define CLK_GOUT_CORE_LHM_AXI_D_CSSYS_CLK 43
+#define CLK_GOUT_CORE_LHM_AXI_D_G3D_CLK 44
+#define CLK_GOUT_CORE_LHM_AXI_D_GNSS_CLK 45
+#define CLK_GOUT_CORE_LHM_AXI_D_SHUB_CLK 46
+#define CLK_GOUT_CORE_LHM_AXI_D_WLBT_CLK 47
+#define CLK_GOUT_CORE_LHS_AXI_D0_MIF_CPU_CLK 48
+#define CLK_GOUT_CORE_LHS_AXI_D0_MIF_CP_CLK 49
+#define CLK_GOUT_CORE_LHS_AXI_D0_MIF_NRT_CLK 50
+#define CLK_GOUT_CORE_LHS_AXI_D0_MIF_RT_CLK 51
+#define CLK_GOUT_CORE_LHS_AXI_D1_MIF_CPU_CLK 52
+#define CLK_GOUT_CORE_LHS_AXI_D1_MIF_CP_CLK 53
+#define CLK_GOUT_CORE_LHS_AXI_D1_MIF_NRT_CLK 54
+#define CLK_GOUT_CORE_LHS_AXI_D1_MIF_RT_CLK 55
+#define CLK_GOUT_CORE_LHS_AXI_P_APM_CLK 56
+#define CLK_GOUT_CORE_LHS_AXI_P_CAM_CLK 57
+#define CLK_GOUT_CORE_LHS_AXI_P_CPUCL0_CLK 58
+#define CLK_GOUT_CORE_LHS_AXI_P_CPUCL1_CLK 59
+#define CLK_GOUT_CORE_LHS_AXI_P_DISPAUD_CLK 60
+#define CLK_GOUT_CORE_LHS_AXI_P_FSYS_CLK 61
+#define CLK_GOUT_CORE_LHS_AXI_P_G2D_CLK 62
+#define CLK_GOUT_CORE_LHS_AXI_P_G3D_CLK 63
+#define CLK_GOUT_CORE_LHS_AXI_P_GNSS_CLK 64
+#define CLK_GOUT_CORE_LHS_AXI_P_ISP_CLK 65
+#define CLK_GOUT_CORE_LHS_AXI_P_MFC_CLK 66
+#define CLK_GOUT_CORE_LHS_AXI_P_MIF0_CLK 67
+#define CLK_GOUT_CORE_LHS_AXI_P_MIF1_CLK 68
+#define CLK_GOUT_CORE_LHS_AXI_P_MODEM_CLK 69
+#define CLK_GOUT_CORE_LHS_AXI_P_PERI_CLK 70
+#define CLK_GOUT_CORE_LHS_AXI_P_SHUB_CLK 71
+#define CLK_GOUT_CORE_LHS_AXI_P_USB_CLK 72
+#define CLK_GOUT_CORE_LHS_AXI_P_VIPX1_CLK 73
+#define CLK_GOUT_CORE_LHS_AXI_P_VIPX2_CLK 74
+#define CLK_GOUT_CORE_LHS_AXI_P_WLBT_CLK 75
+#define CLK_GOUT_CORE_PDMA_CORE_ACLK_PDMA0 76
+#define CLK_GOUT_CORE_PGEN_LITE_SIREX_CLK 77
+#define CLK_GOUT_CORE_PGEN_PDMA_CLK 78
+#define CLK_GOUT_CORE_PPCFW_G3D_ACLK 79
+#define CLK_GOUT_CORE_PPCFW_G3D_PCLK 80
+#define CLK_GOUT_CORE_PPFW_CORE_MEM0_CLK 81
+#define CLK_GOUT_CORE_PPFW_CORE_MEM1_CLK 82
+#define CLK_GOUT_CORE_PPFW_CORE_PERI_CLK 83
+#define CLK_GOUT_CORE_PPMU_ACE_CPUCL0_ACLK 84
+#define CLK_GOUT_CORE_PPMU_ACE_CPUCL0_PCLK 85
+#define CLK_GOUT_CORE_PPMU_ACE_CPUCL1_ACLK 86
+#define CLK_GOUT_CORE_PPMU_ACE_CPUCL1_PCLK 87
+#define CLK_GOUT_CORE_BUSD_CLK 88
+#define CLK_GOUT_CORE_BUSP_G3D_OCC_CLK 89
+#define CLK_GOUT_CORE_BUSP_CLK 90
+#define CLK_GOUT_CORE_BUSP_OCC_CLK 91
+#define CLK_GOUT_CORE_CCI_CLK 92
+#define CLK_GOUT_CORE_CCI_OCC_CLK 93
+#define CLK_GOUT_CORE_G3D_CLK 94
+#define CLK_GOUT_CORE_G3D_OCC_CLK 95
+#define CLK_GOUT_CORE_GIC_CLK 96
+#define CLK_GOUT_CORE_OSCCLK_CLK 97
+#define CLK_GOUT_CORE_SFR_APBIF_CMU_TOPC_PCLK 98
+#define CLK_GOUT_CORE_SIREX_ACLK 99
+#define CLK_GOUT_CORE_SIREX_PCLK 100
+#define CLK_GOUT_CORE_SPDMA_CORE_ACLK_PDMA1 101
+#define CLK_GOUT_CORE_SYSREG_PCLK 102
+#define CLK_GOUT_CORE_TREX_D_ACLK 103
+#define CLK_GOUT_CORE_TREX_D_CCLK 104
+#define CLK_GOUT_CORE_TREX_D_GCLK 105
+#define CLK_GOUT_CORE_TREX_D_PCLK 106
+#define CLK_GOUT_CORE_TREX_D_NRT_ACLK 107
+#define CLK_GOUT_CORE_TREX_D_NRT_PCLK 108
+#define CLK_GOUT_CORE_TREX_P_ACLK_P_CORE 109
+#define CLK_GOUT_CORE_TREX_P_CCLK_P_CORE 110
+#define CLK_GOUT_CORE_TREX_P_PCLK 111
+#define CLK_GOUT_CORE_TREX_P_PCLK_P_CORE 112
+#define CLK_GOUT_CORE_XIU_D_ACLK 113
+
+/* CMU_CPUCL0 PLLs */
+#define CLK_FOUT_CPUCL0_PLL 1
+
+/* CMU_CPUCL0 muxes */
+#define CLK_MOUT_PLL_CPUCL0_DBG_USER 2
+#define CLK_MOUT_PLL_CPUCL0_SWITCH_USER 3
+#define CLK_MOUT_CLK_CPUCL0_PLL 4
+
+/* CMU_CPUCL0 dividers */
+#define CLK_DOUT_CLK_CLUSTER0_ACLK 5
+#define CLK_DOUT_CLK_CLUSTER0_CNTCLK 6
+#define CLK_DOUT_CLK_CLUSTER0_PCLKDBG 7
+#define CLK_DOUT_CLK_CPUCL0_CMUREF 8
+#define CLK_DOUT_CLK_CPUCL0_CPU 9
+#define CLK_DOUT_CLK_CPUCL0_PCLK 10
+
+/* CMU_CPUCL0 gates */
+#define CLK_GOUT_CLK_CPUCL0_CMU_PCLK 11
+#define CLK_GOUT_CLK_CPUCL0_HPM_TARGETCLK_C 12
+#define CLK_GOUT_CLK_CPUCL0_OSCCLK_CLK 13
+#define CLK_GOUT_CLK_CLUSTER0_CPU 14
+#define CLK_GOUT_CPUCL0_ADM_APB_G_CSSYS_CORE_PCLKM 15
+#define CLK_GOUT_CPUCL0_ADS_AHB_G_CSSYS_FSYS_HCLKS 16
+#define CLK_GOUT_CPUCL0_ADS_APB_G_CSSYS_CPUCL1_PCLKS 17
+#define CLK_GOUT_CPUCL0_ADS_APB_G_P8Q_PCLKS 18
+#define CLK_GOUT_CPUCL0_AD_APB_P_DUMP_PC_CPUCL0_PCLKM 19
+#define CLK_GOUT_CPUCL0_AD_APB_P_DUMP_PC_CPUCL1_PCLKM 20
+#define CLK_GOUT_CPUCL0_BUSIF_HPMCPUCL0_PCLK 21
+#define CLK_GOUT_CPUCL0_CSSYS_DBG_PCLKDBG 22
+#define CLK_GOUT_CPUCL0_DUMP_PC_CPUCL0_PCLK 23
+#define CLK_GOUT_CPUCL0_DUMP_PC_CPUCL1_PCLK 24
+#define CLK_GOUT_CPUCL0_LHM_AXI_P_CPUCL0_CLK 25
+#define CLK_GOUT_CPUCL0_LHS_AXI_D_CSSYS_CLK 26
+#define CLK_GOUT_CPUCL0_DBG_CLK 27
+#define CLK_GOUT_CPUCL0_PCLK_CLK 28
+#define CLK_GOUT_CPUCL0_SECJTAG_CLK 29
+#define CLK_GOUT_CPUCL0_SYSREG_PCLK 30
+
+/* CMU_CPUCL1 PLLs */
+#define CLK_FOUT_CPUCL1_PLL 1
+
+/* CMU_CPUCL1 muxes */
+#define CLK_MOUT_PLL_CPUCL1_SWITCH_USER 2
+#define CLK_MOUT_CLK_CPUCL1_PLL 3
+
+/* CMU_CPUCL1 dividers */
+#define CLK_DOUT_CLK_CLUSTER1_ACLK 4
+#define CLK_DOUT_CLK_CLUSTER1_CNTCLK 5
+#define CLK_DOUT_CLK_CPUCL1_CMUREF 6
+#define CLK_DOUT_CLK_CPUCL1_CPU 7
+#define CLK_DOUT_CLK_CPUCL1_PCLK 8
+#define CLK_DOUT_CLK_CPUCL1_PCLKDBG 9
+
+/* CMU_CPUCL1 gates */
+#define CLK_GOUT_CLK_CPUCL1_CMU_PCLK 10
+#define CLK_GOUT_CLK_CPUCL1_HPM_TARGETCLK_C 11
+#define CLK_GOUT_CLK_CPUCL1_OSCCLK_CLK 12
+#define CLK_GOUT_CLK_CLUSTER1_CPU 13
+#define CLK_GOUT_CPUCL1_ADM_APB_G_CSSYS_CPUCL1_PCLKM 14
+#define CLK_GOUT_CPUCL1_BUSIF_HPMCPUCL1_PCLK 15
+#define CLK_GOUT_CPUCL1_LHM_AXI_P_CPUCL1_CLK 16
+#define CLK_GOUT_CPUCL1_LHS_ACE_D_CLK 17
+#define CLK_GOUT_CPUCL1_ACLK_CLK 18
+#define CLK_GOUT_CPUCL1_PCLKDBG_CLK 19
+#define CLK_GOUT_CPUCL1_PCLK_CLK 20
+#define CLK_GOUT_CPUCL1_SYSREG_PCLK 21
+
+/* CMU_DISPAUD PLLs */
+#define CLK_FOUT_AUD_PLL 1
+
+/* CMU_DISPAUD muxes */
+#define CLK_MOUT_PLL_DISPAUD_AUD_USER 2
+#define CLK_MOUT_PLL_DISPAUD_CPU_USER 3
+#define CLK_MOUT_PLL_DISPAUD_DISP_USER 4
+#define CLK_MOUT_CLK_AUD_BUS 5
+#define CLK_MOUT_CLK_AUD_CPU 6
+#define CLK_MOUT_CLK_AUD_CPU_HCH 7
+#define CLK_MOUT_CLK_AUD_FM 8
+#define CLK_MOUT_CLK_AUD_UAIF0 9
+#define CLK_MOUT_CLK_AUD_UAIF1 10
+#define CLK_MOUT_CLK_AUD_UAIF2 11
+
+/* CMU_DISPAUD dividers */
+#define CLK_DOUT_CLK_AUD_AUDIF 12
+#define CLK_DOUT_CLK_AUD_BUS 13
+#define CLK_DOUT_CLK_AUD_CPU 14
+#define CLK_DOUT_CLK_AUD_CPU_ACLK 15
+#define CLK_DOUT_CLK_AUD_CPU_PCLKDBG 16
+#define CLK_DOUT_CLK_AUD_DSIF 17
+#define CLK_DOUT_CLK_AUD_FM 18
+#define CLK_DOUT_CLK_AUD_FM_SPDY 19
+#define CLK_DOUT_CLK_AUD_UAIF0 20
+#define CLK_DOUT_CLK_AUD_UAIF1 21
+#define CLK_DOUT_CLK_AUD_UAIF2 22
+#define CLK_DOUT_CLK_DISPAUD_BUSP 23
+
+/* CMU_DISPAUD gates */
+#define CLK_GOUT_CLK_DISPAUD_ABOX_BCLK_UAIF0 24
+#define CLK_GOUT_CLK_DISPAUD_ABOX_BCLK_UAIF1 25
+#define CLK_GOUT_CLK_DISPAUD_ABOX_BCLK_UAIF2 26
+#define CLK_GOUT_CLK_DISPAUD_CMU_PCLK 27
+#define CLK_GOUT_CLK_DISPAUD_CLK_AUD_UAIF0_CLK 28
+#define CLK_GOUT_CLK_DISPAUD_CLK_AUD_UAIF1_CLK 29
+#define CLK_GOUT_CLK_DISPAUD_CLK_AUD_UAIF2_CLK 30
+#define CLK_GOUT_CLK_DISPAUD_OSCCLK_CLK 31
+#define CLK_GOUT_DISPAUD_ABOX_ACLK 32
+#define CLK_GOUT_DISPAUD_ABOX_BCLK_DSIF 33
+#define CLK_GOUT_DISPAUD_ABOX_BCLK_SPDY 34
+#define CLK_GOUT_DISPAUD_ABOX_CCLK_ASB 35
+#define CLK_GOUT_DISPAUD_ABOX_CCLK_CA7 36
+#define CLK_GOUT_DISPAUD_ABOX_CCLK_DBG 37
+#define CLK_GOUT_DISPAUD_ABOX_OSC_SPDY 38
+#define CLK_GOUT_DISPAUD_AXI_US_32TO128_ACLK 39
+#define CLK_GOUT_DISPAUD_CLK_DISPAUD_AUD 40
+#define CLK_GOUT_DISPAUD_CLK_DISPAUD_DISP 41
+#define CLK_GOUT_DISPAUD_BTM_ABOX_ACLK 42
+#define CLK_GOUT_DISPAUD_BTM_ABOX_PCLK 43
+#define CLK_GOUT_DISPAUD_BTM_DPU_ACLK 44
+#define CLK_GOUT_DISPAUD_BTM_DPU_PCLK 45
+#define CLK_GOUT_DISPAUD_DFTMUX_AUD_CODEC_MCLK 46
+#define CLK_GOUT_DISPAUD_DPU_ACLK_DECON 47
+#define CLK_GOUT_DISPAUD_DPU_ACLK_DMA 48
+#define CLK_GOUT_DISPAUD_DPU_ACLK_DPP 49
+#define CLK_GOUT_DISPAUD_GPIO_DISPAUD_PCLK 50
+#define CLK_GOUT_DISPAUD_LHM_AXI_P_DISPAUD_CLK 51
+#define CLK_GOUT_DISPAUD_LHS_ACEL_D_DPU_CLK 52
+#define CLK_GOUT_DISPAUD_LHS_AXI_D_ABOX_CLK 53
+#define CLK_GOUT_DISPAUD_PERI_AXI_ASB_ACLKM 54
+#define CLK_GOUT_DISPAUD_PERI_AXI_ASB_PCLK 55
+#define CLK_GOUT_DISPAUD_PPMU_ABOX_ACLK 56
+#define CLK_GOUT_DISPAUD_PPMU_ABOX_PCLK 57
+#define CLK_GOUT_DISPAUD_PPMU_DPU_ACLK 58
+#define CLK_GOUT_DISPAUD_PPMU_DPU_PCLK 59
+#define CLK_GOUT_DISPAUD_CLK_AUD_CPU_ACLK_CLK 60
+#define CLK_GOUT_DISPAUD_CLK_AUD_CPU_CLKIN_CLK 61
+#define CLK_GOUT_DISPAUD_CLK_AUD_CPU_PCLKDBG_CLK 62
+#define CLK_GOUT_DISPAUD_CLK_AUD_DSIF_CLK 63
+#define CLK_GOUT_DISPAUD_CLK_AUD_CLK 64
+#define CLK_GOUT_DISPAUD_CLK_BUSP_CLK 65
+#define CLK_GOUT_DISPAUD_CLK_DISP_CLK 66
+#define CLK_GOUT_DISPAUD_SMMU_ABOX_CLK 67
+#define CLK_GOUT_DISPAUD_SMMU_DPU_CLK 68
+#define CLK_GOUT_DISPAUD_SYSREG_PCLK 69
+#define CLK_GOUT_DISPAUD_WDT_AUD_PCLK 70
+
+/* CMU_FSYS muxes */
+#define CLK_MOUT_PLL_FSYS_BUS_USER 1
+#define CLK_MOUT_PLL_FSYS_MMC_CARD_USER 2
+#define CLK_MOUT_PLL_FSYS_MMC_EMBD_USER 3
+#define CLK_MOUT_PLL_FSYS_UFS_EMBD_USER 4
+
+/* CMU_FSYS gates */
+#define CLK_GOUT_FSYS_CMU_PCLK 5
+#define CLK_GOUT_FSYS_OSCCLK_CLK 6
+#define CLK_GOUT_FSYS_ADM_AHB_SSS_HCLKM 7
+#define CLK_GOUT_FSYS_BTM_ACLK 8
+#define CLK_GOUT_FSYS_BTM_PCLK 9
+#define CLK_GOUT_FSYS_GPIO_PCLK 10
+#define CLK_GOUT_FSYS_LHM_AXI_P_CLK 11
+#define CLK_GOUT_FSYS_LHS_ACEL_D_CLK 12
+#define CLK_GOUT_FSYS_MMC_CARD_ACLK 13
+#define CLK_GOUT_FSYS_MMC_CARD_SDCLKIN 14
+#define CLK_GOUT_FSYS_MMC_EMBD_ACLK 15
+#define CLK_GOUT_FSYS_MMC_EMBD_SDCLKIN 16
+#define CLK_GOUT_FSYS_PGEN_LITE_CLK 17
+#define CLK_GOUT_FSYS_PPMU_ACLK 18
+#define CLK_GOUT_FSYS_PPMU_PCLK 19
+#define CLK_GOUT_FSYS_BUS_CLK 20
+#define CLK_GOUT_FSYS_SYSREG_PCLK 21
+#define CLK_GOUT_FSYS_UFS_EMBD_ACLK 22
+#define CLK_GOUT_FSYS_UFS_EMBD_CLK_UNIPRO 23
+#define CLK_GOUT_FSYS_UFS_EMBD_FMP_CLK 24
+#define CLK_GOUT_FSYS_XIU_D_ACLK 25
+
+/* CMU_G2D muxes */
+#define CLK_MOUT_PLL_G2D_G2D_USER 1
+#define CLK_MOUT_PLL_G2D_MSCL_USER 2
+
+/* CMU_G2D dividers */
+#define CLK_DOUT_CLK_G2D_BUSP 3
+
+/* CMU_G2D gates */
+#define CLK_GOUT_CLK_G2D_CMU_PCLK 4
+#define CLK_GOUT_CLK_G2D_OSCCLK_CLK 5
+#define CLK_GOUT_G2D_AS_AXI_JPEG_ACLKM 6
+#define CLK_GOUT_G2D_AS_AXI_JPEG_ACLKS 7
+#define CLK_GOUT_G2D_AS_AXI_MSCL_ACLKM 8
+#define CLK_GOUT_G2D_AS_AXI_MSCL_ACLKS 9
+#define CLK_GOUT_G2D_CLK_G2D_G2D 10
+#define CLK_GOUT_G2D_CLK_G2D_MSCL 11
+#define CLK_GOUT_G2D_BTM_G2D_ACLK 12
+#define CLK_GOUT_G2D_BTM_G2D_PCLK 13
+#define CLK_GOUT_G2D_G2D_ACLK 14
+#define CLK_GOUT_G2D_JPEG_FIMP_CLK 15
+#define CLK_GOUT_G2D_LHM_AXI_P_CLK 16
+#define CLK_GOUT_G2D_LHS_ACEL_D_CLK 17
+#define CLK_GOUT_G2D_MSCL_ACLK 18
+#define CLK_GOUT_G2D_PGEN100_LITE_CLK 19
+#define CLK_GOUT_G2D_PPMU_ACLK 20
+#define CLK_GOUT_G2D_PPMU_PCLK 21
+#define CLK_GOUT_G2D_BUSP_CLK 22
+#define CLK_GOUT_G2D_SYSMMU_CLK 23
+#define CLK_GOUT_G2D_SYSREG_PCLK 24
+#define CLK_GOUT_G2D_XIU_D_MSCL_ACLK 25
+
+/* CMU_G3D PLLs */
+#define CLK_FOUT_G3D_PLL 1
+
+/* CMU_G3D muxes */
+#define CLK_MOUT_G3D_SWITCH_USER 2
+#define CLK_MOUT_CLK_G3D_BUSD 3
+
+/* CMU_G3D dividers */
+#define CLK_DOUT_CLK_G3D_BUSD 4
+#define CLK_DOUT_CLK_G3D_BUSP 5
+
+/* CMU_G3D gates */
+#define CLK_GOUT_CLK_G3D_CMU_PCLK 6
+#define CLK_GOUT_CLK_G3D_G3D_CLK 7
+#define CLK_GOUT_CLK_G3D_HPM_TARGETCLK_C 8
+#define CLK_GOUT_CLK_G3D_OSCCLK_CLK 9
+#define CLK_GOUT_G3D_BTM_G3D_ACLK 10
+#define CLK_GOUT_G3D_BTM_G3D_PCLK 11
+#define CLK_GOUT_G3D_BUSIF_HPMG3D_PCLK 12
+#define CLK_GOUT_G3D_GRAY2BIN_G3D_CLK 13
+#define CLK_GOUT_G3D_LHM_AXI_G3DSFR_CLK 14
+#define CLK_GOUT_G3D_LHM_AXI_P_G3D_CLK 15
+#define CLK_GOUT_G3D_LHS_AXI_D_G3D_CLK 16
+#define CLK_GOUT_G3D_LHS_AXI_G3DSFR_CLK 17
+#define CLK_GOUT_G3D_PGEN_LITE_G3D_CLK 18
+#define CLK_GOUT_G3D_BUSD_CLK 19
+#define CLK_GOUT_G3D_BUSP_CLK 20
+#define CLK_GOUT_G3D_SYSREG_PCLK 21
+
+/* CMU_PERI muxes */
+#define CLK_MOUT_PLL_PERI_BUS_USER 1
+#define CLK_MOUT_PLL_PERI_IP_USER 2
+#define CLK_MOUT_PLL_PERI_UART_USER 3
+
+/* CMU_PERI dividers */
+#define CLK_DOUT_CLK_PERI_I2C 4
+#define CLK_DOUT_CLK_PERI_SPI0 5
+#define CLK_DOUT_CLK_PERI_SPI1 6
+#define CLK_DOUT_CLK_PERI_SPI2 7
+#define CLK_DOUT_CLK_PERI_USI_I2C 8
+#define CLK_DOUT_CLK_PERI_USI_USI 9
+
+/* CMU_PERI gates */
+#define CLK_GOUT_CLK_PERI_I2C 10
+#define CLK_GOUT_CLK_PERI_SPI0 11
+#define CLK_GOUT_CLK_PERI_SPI1 12
+#define CLK_GOUT_CLK_PERI_SPI2 13
+#define CLK_GOUT_CLK_PERI_USI_I2C 14
+#define CLK_GOUT_CLK_PERI_USI_USI 15
+#define CLK_GOUT_PERI_AXI2AHB_MSD32_ACLK 16
+#define CLK_GOUT_PERI_BUSIF_TMU_PCLK 17
+#define CLK_GOUT_PERI_CAMI2C_0_IPCLK 18
+#define CLK_GOUT_PERI_CAMI2C_0_PCLK 19
+#define CLK_GOUT_PERI_CAMI2C_1_IPCLK 20
+#define CLK_GOUT_PERI_CAMI2C_1_PCLK 21
+#define CLK_GOUT_PERI_CAMI2C_2_IPCLK 22
+#define CLK_GOUT_PERI_CAMI2C_2_PCLK 23
+#define CLK_GOUT_PERI_CAMI2C_3_IPCLK 24
+#define CLK_GOUT_PERI_CAMI2C_3_PCLK 25
+#define CLK_GOUT_PERI_I2C_0_PCLK 26
+#define CLK_GOUT_PERI_I2C_1_PCLK 27
+#define CLK_GOUT_PERI_I2C_2_PCLK 28
+#define CLK_GOUT_PERI_I2C_3_PCLK 29
+#define CLK_GOUT_PERI_I2C_4_PCLK 30
+#define CLK_GOUT_PERI_I2C_5_PCLK 31
+#define CLK_GOUT_PERI_I2C_6_PCLK 32
+#define CLK_GOUT_PERI_GPIO_PCLK 33
+#define CLK_GOUT_PERI_LHM_AXI_P_PERI_CLK 34
+#define CLK_GOUT_PERI_MCT_PCLK 35
+#define CLK_GOUT_PERI_OTP_CON_TOP_PCLK 36
+#define CLK_GOUT_PERI_PWM_MOTOR_PCLK_S0 37
+#define CLK_GOUT_PERI_BUS_CLK 38
+#define CLK_GOUT_PERI_I2C_CLK 39
+#define CLK_GOUT_PERI_SPI_0_CLK 40
+#define CLK_GOUT_PERI_SPI_1_CLK 41
+#define CLK_GOUT_PERI_SPI_2_CLK 42
+#define CLK_GOUT_PERI_UART_CLK 43
+#define CLK_GOUT_PERI_USI00_I2C_CLK 44
+#define CLK_GOUT_PERI_USI00_USI_CLK 45
+#define CLK_GOUT_PERI_SPI_0_PCLK 46
+#define CLK_GOUT_PERI_SPI_0_IPCLK 47
+#define CLK_GOUT_PERI_SPI_1_PCLK 48
+#define CLK_GOUT_PERI_SPI_1_IPCLK 49
+#define CLK_GOUT_PERI_SPI_2_PCLK 50
+#define CLK_GOUT_PERI_SPI_2_IPCLK 51
+#define CLK_GOUT_PERI_SYSREG_PCLK 52
+#define CLK_GOUT_PERI_UART_IPCLK 53
+#define CLK_GOUT_PERI_UART_PCLK 54
+#define CLK_GOUT_PERI_USI00_I2C_IPCLK 55
+#define CLK_GOUT_PERI_USI00_I2C_PCLK 56
+#define CLK_GOUT_PERI_USI00_USI_IPCLK 57
+#define CLK_GOUT_PERI_USI00_USI_PCLK 58
+#define CLK_GOUT_PERI_WDT_CLUSTER0_PCLK 59
+#define CLK_GOUT_PERI_WDT_CLUSTER1_PCLK 60
--
2.47.3
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