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Message-ID: <20250915-exynos9610-clocks-v1-4-3f615022b178@chimac.ro>
Date: Sun, 14 Sep 2025 21:19:57 +0000
From: Alexandru Chimac <alex@...mac.ro>
To: Krzysztof Kozlowski <krzk@...nel.org>, Sylwester Nawrocki <s.nawrocki@...sung.com>, Chanwoo Choi <cw00.choi@...sung.com>, Alim Akhtar <alim.akhtar@...sung.com>, Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Alexandru Chimac <alexchimac@...tonmail.com>, Krzysztof Kozlowski <krzk+dt@...nel.org>
Cc: linux-samsung-soc@...r.kernel.org, linux-clk@...r.kernel.org, devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, Alexandru Chimac <alex@...mac.ro>
Subject: [PATCH 4/8] arm64: dts: exynos9610: Enable clock support
Add CMU (Clock Management Unit) nodes and required
fixed clocks.
Signed-off-by: Alexandru Chimac <alex@...mac.ro>
---
arch/arm64/boot/dts/exynos/exynos9610-gta4xl.dts | 1 +
arch/arm64/boot/dts/exynos/exynos9610.dtsi | 205 +++++++++++++++++++++++
2 files changed, 206 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos9610-gta4xl.dts b/arch/arm64/boot/dts/exynos/exynos9610-gta4xl.dts
index f455af22ff872c6f07b9bcfc68b1ae1f45d0def3..1a09d5e8ebaa130e9cd0b7f3266ee2c9dac4cf9a 100644
--- a/arch/arm64/boot/dts/exynos/exynos9610-gta4xl.dts
+++ b/arch/arm64/boot/dts/exynos/exynos9610-gta4xl.dts
@@ -10,6 +10,7 @@
#include "exynos9610.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
+#include <dt-bindings/clock/samsung,exynos9610.h>
/ {
compatible = "samsung,gta4xl", "samsung,exynos9610";
diff --git a/arch/arm64/boot/dts/exynos/exynos9610.dtsi b/arch/arm64/boot/dts/exynos/exynos9610.dtsi
index 852f7111e5cdfd82b5afc350792e8b539fe87d39..2a15986c459d6af9f83362c27cdcc3a2646c256b 100644
--- a/arch/arm64/boot/dts/exynos/exynos9610.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos9610.dtsi
@@ -6,6 +6,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/samsung,exynos9610.h>
/ {
compatible = "samsung,exynos9610";
@@ -161,6 +162,41 @@ oscclk: clock-osc {
clock-frequency = <26000000>;
};
+ dll_dco: clock-dll-dco {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "dll_dco";
+ clock-frequency = <360000000>;
+ };
+
+ oscclk_rco_cmgp: clock-osc-rco {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "oscclk_rco";
+ clock-frequency = <30000000>;
+ };
+
+ ioclk_audiocdclk0: clock-audiocdclk0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "ioclk_audiocdclk0";
+ clock-frequency = <10000000>;
+ };
+
+ ioclk_audiocdclk1: clock-audiocdclk1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "ioclk_audiocdclk1";
+ clock-frequency = <100000000>;
+ };
+
+ tick_usb: clock-tick-usb {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "tick_usb";
+ clock-frequency = <60000000>;
+ };
+
soc: soc@0 {
compatible = "simple-bus";
ranges = <0x0 0x0 0x0 0x20000000>;
@@ -174,12 +210,81 @@ chipid@...00000 {
reg = <0x10000000 0x100>;
};
+ cmu_peri: clock-controller@...30000 {
+ compatible = "samsung,exynos9610-cmu-peri";
+ reg = <0x10030000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_CMU_PERI_BUS>,
+ <&cmu_top CLK_DOUT_CMU_PERI_IP>,
+ <&cmu_top CLK_DOUT_CMU_PERI_UART>;
+ clock-names = "oscclk",
+ "dout_cmu_peri_bus",
+ "dout_cmu_peri_ip",
+ "dout_cmu_peri_uart";
+ };
+
+ cmu_cpucl1: clock-controller@...0800000 {
+ compatible = "samsung,exynos9610-cmu-cpucl1";
+ reg = <0x10800000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_CMU_CPUCL1_SWITCH>,
+ <&cmu_top CLK_DOUT_CMU_HPM>;
+ clock-names = "oscclk",
+ "dout_cmu_cpucl1_switch",
+ "dout_cmu_hpm";
+ };
+
+ cmu_cpucl0: clock-controller@...0900000 {
+ compatible = "samsung,exynos9610-cmu-cpucl0";
+ reg = <0x10900000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_CMU_CPUCL0_DBG>,
+ <&cmu_top CLK_DOUT_CMU_CPUCL0_SWITCH>,
+ <&cmu_top CLK_DOUT_CMU_HPM>;
+ clock-names = "oscclk",
+ "dout_cmu_cpucl0_dbg",
+ "dout_cmu_cpucl0_switch",
+ "dout_cmu_hpm";
+ };
+
pinctrl_shub: pinctrl@...80000 {
compatible = "samsung,exynos9610-pinctrl";
reg = <0x11080000 0x1000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
};
+ cmu_g3d: clock-controller@...30000 {
+ compatible = "samsung,exynos9610-cmu-g3d";
+ reg = <0x11430000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_CMU_G3D_SWITCH>,
+ <&cmu_top CLK_DOUT_CMU_HPM>;
+ clock-names = "oscclk",
+ "dout_cmu_g3d_switch",
+ "dout_cmu_hpm";
+ };
+
+ cmu_apm: clock-controller@...00000 {
+ compatible = "samsung,exynos9610-cmu-apm";
+ reg = <0x11800000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>,
+ <&dll_dco>,
+ <&cmu_top CLK_DOUT_CMU_APM_BUS>;
+ clock-names = "oscclk",
+ "dll_dco",
+ "dout_cmu_apm_bus";
+ };
+
pinctrl_alive: pinctrl@...50000 {
compatible = "samsung,exynos9610-pinctrl";
reg = <0x11850000 0x1000>;
@@ -191,11 +296,48 @@ wakeup-interrupt-controller {
};
};
+ cmu_cmgp: clock-controller@...00000 {
+ compatible = "samsung,exynos9610-cmu-cmgp";
+ reg = <0x11c00000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>,
+ <&oscclk_rco_cmgp>,
+ <&cmu_apm CLK_GOUT_CMU_CMGP_BUS>;
+ clock-names = "oscclk",
+ "oscclk_rco",
+ "gout_cmu_cmgp_bus";
+ };
+
pinctrl_cmgp: pinctrl@...20000 {
compatible = "samsung,exynos9610-pinctrl";
reg = <0x11c20000 0x1000>;
};
+ cmu_core: clock-controller@...f0000 {
+ compatible = "samsung,exynos9610-cmu-core";
+ reg = <0x120f0000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_CMU_CORE_BUS>,
+ <&cmu_top CLK_DOUT_CMU_CORE_CCI>,
+ <&cmu_top CLK_DOUT_CMU_CORE_G3D>;
+ clock-names = "oscclk",
+ "dout_cmu_core_bus",
+ "dout_cmu_core_cci",
+ "dout_cmu_core_g3d";
+ };
+
+ cmu_top: clock-controller@...00000 {
+ compatible = "samsung,exynos9610-cmu-top";
+ reg = <0x12100000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>;
+ clock-names = "oscclk";
+ };
+
gic: interrupt-controller@...00000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@@ -209,6 +351,37 @@ gic: interrupt-controller@...00000 {
IRQ_TYPE_LEVEL_HIGH)>;
};
+ cmu_g2d: clock-controller@...00000 {
+ compatible = "samsung,exynos9610-cmu-g2d";
+ reg = <0x12e00000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_CMU_G2D_G2D>,
+ <&cmu_top CLK_DOUT_CMU_G2D_MSCL>;
+
+ clock-names = "oscclk",
+ "dout_cmu_g2d_g2d",
+ "dout_cmu_g2d_mscl";
+ };
+
+ cmu_fsys: clock-controller@...00000 {
+ compatible = "samsung,exynos9610-cmu-fsys";
+ reg = <0x13400000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_CMU_FSYS_BUS>,
+ <&cmu_top CLK_DOUT_CMU_FSYS_MMC_CARD>,
+ <&cmu_top CLK_DOUT_CMU_FSYS_MMC_EMBD>,
+ <&cmu_top CLK_DOUT_CMU_FSYS_UFS_EMBD>;
+ clock-names = "oscclk",
+ "dout_cmu_fsys_bus",
+ "dout_cmu_fsys_mmc_card",
+ "dout_cmu_fsys_mmc_embd",
+ "dout_cmu_fsys_ufs_embd";
+ };
+
pinctrl_fsys: pinctrl@...90000 {
compatible = "samsung,exynos9610-pinctrl";
reg = <0x13490000 0x1000>;
@@ -221,6 +394,38 @@ pinctrl_top: pinctrl@...b0000 {
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
};
+ cmu_cam: clock-controller@...00000 {
+ compatible = "samsung,exynos9610-cmu-cam";
+ reg = <0x14500000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_CMU_CAM_BUS>;
+ clock-names = "oscclk",
+ "dout_cmu_cam_bus";
+ };
+
+ cmu_dispaud: clock-controller@...80000 {
+ compatible = "samsung,exynos9610-cmu-dispaud";
+ reg = <0x14980000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>,
+ <&ioclk_audiocdclk0>,
+ <&ioclk_audiocdclk1>,
+ <&tick_usb>,
+ <&cmu_top CLK_DOUT_CMU_DISPAUD_AUD>,
+ <&cmu_top CLK_DOUT_CMU_DISPAUD_CPU>,
+ <&cmu_top CLK_DOUT_CMU_DISPAUD_DISP>;
+ clock-names = "oscclk",
+ "ioclk_audiocdclk0",
+ "ioclk_audiocdclk1",
+ "tick_usb",
+ "dout_cmu_dispaud_aud",
+ "dout_cmu_dispaud_cpu",
+ "dout_cmu_dispaud_disp";
+ };
+
pinctrl_dispaud: pinctrl@...60000 {
compatible = "samsung,exynos9610-pinctrl";
reg = <0x14a60000 0x1000>;
--
2.47.3
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