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Message-ID: <aMgh1L/TcrNvaHtL@lizhi-Precision-Tower-5810>
Date: Mon, 15 Sep 2025 10:25:24 -0400
From: Frank Li <Frank.li@....com>
To: Richard Zhu <hongxing.zhu@....com>
Cc: l.stach@...gutronix.de, lpieralisi@...nel.org, kwilczynski@...nel.org,
mani@...nel.org, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, bhelgaas@...gle.com, shawnguo@...nel.org,
s.hauer@...gutronix.de, kernel@...gutronix.de, festevam@...il.com,
linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
devicetree@...r.kernel.org, imx@...ts.linux.dev,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5 1/3] dt-bindings: PCI: dwc: Add one more reference
clock
On Mon, Sep 15, 2025 at 11:53:46AM +0800, Richard Zhu wrote:
> Add one more reference clock "extref" to for a reference clock that
> comes from external crystal oscillator.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@....com>
Reviewed-by: Frank Li <Frank.Li@....com>
> ---
> .../devicetree/bindings/pci/snps,dw-pcie-common.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> index 34594972d8db..0134a759185e 100644
> --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> @@ -105,6 +105,12 @@ properties:
> define it with this name (for instance pipe, core and aux can
> be connected to a single source of the periodic signal).
> const: ref
> + - description:
> + Some dwc wrappers (like i.MX95 PCIes) have two reference clock
> + inputs, one from an internal PLL, the other from an off-chip crystal
> + oscillator. If present, 'extref' refers to a reference clock from
> + an external oscillator.
> + const: extref
> - description:
> Clock for the PHY registers interface. Originally this is
> a PHY-viewport-based interface, but some platform may have
> --
> 2.37.1
>
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