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Message-ID:
<CH2PPF4D26F8E1CBFECCE8056787FE017B1A215A@CH2PPF4D26F8E1C.namprd07.prod.outlook.com>
Date: Mon, 15 Sep 2025 03:43:05 +0000
From: Manikandan Karunakaran Pillai <mpillai@...ence.com>
To: Manivannan Sadhasivam <mani@...nel.org>,
"hans.zhang@...tech.com"
<hans.zhang@...tech.com>
CC: "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
"lpieralisi@...nel.org"
<lpieralisi@...nel.org>,
"kw@...ux.com" <kw@...ux.com>, "robh@...nel.org"
<robh@...nel.org>,
"kwilczynski@...nel.org" <kwilczynski@...nel.org>,
"krzk+dt@...nel.org" <krzk+dt@...nel.org>,
"conor+dt@...nel.org"
<conor+dt@...nel.org>,
"fugang.duan@...tech.com" <fugang.duan@...tech.com>,
"guoyin.chen@...tech.com" <guoyin.chen@...tech.com>,
"peter.chen@...tech.com"
<peter.chen@...tech.com>,
"cix-kernel-upstream@...tech.com"
<cix-kernel-upstream@...tech.com>,
"linux-pci@...r.kernel.org"
<linux-pci@...r.kernel.org>,
"devicetree@...r.kernel.org"
<devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org"
<linux-kernel@...r.kernel.org>,
Milind Parab <mparab@...ence.com>
Subject: RE: [PATCH v9 03/14] PCI: cadence: Add register definitions for High
Perf Architecture (HPA)
Hi Mani,
Can you pls advise on my query on your comment below ?
Manikandan Pillai
>>
>>No need to split this into a separate patch. Squash it with the patch that adds
>>the code consuming these.
>>
>>- Mani
>
>Some of the earlier comments on the same patch set required that
>moves/splitting of a file be in a separate patch and also the size of the patch be
>kept to a manageable size. Please let me know if you would still like this patch
>to be clubbed into a bigger patch.
>
>Manikandan Pillai
>>
>>> ---
>>> .../cadence/pcie-cadence-hpa-regs.h | 192 ++++++++++++++++++
>>> drivers/pci/controller/cadence/pcie-cadence.h | 1 +
>>> 2 files changed, 193 insertions(+)
>>> create mode 100644 drivers/pci/controller/cadence/pcie-cadence-hpa-
>regs.h
>>>
>>> diff --git a/drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h
>>b/drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h
>>> new file mode 100644
>>> index 000000000000..7ef87cf96836
>>> --- /dev/null
>>> +++ b/drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h
>>> @@ -0,0 +1,192 @@
>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>> +/*
>>> + * Cadence PCIe controller driver.
>>> + *
>>> + * Copyright (c) 2019, Cadence Design Systems
>>> + * Author: Manikandan K Pillai <mpillai@...ence.com>
>>> + */
>>> +#ifndef _PCIE_CADENCE_HPA_REGS_H
>>> +#define _PCIE_CADENCE_HPA_REGS_H
>>> +
>>> +#include <linux/kernel.h>
>>> +#include <linux/pci.h>
>>> +#include <linux/pci-epf.h>
>>> +#include <linux/phy/phy.h>
>>> +#include <linux/bitfield.h>
>>> +
>>> +/* High Performance Architecture (HPA) PCIe controller registers */
>>> +#define CDNS_PCIE_HPA_IP_REG_BANK 0x01000000
>>> +#define CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK 0x01003C00
>>> +#define CDNS_PCIE_HPA_IP_AXI_MASTER_COMMON 0x01020000
>>> +
>>> +/* Address Translation Registers */
>>> +#define CDNS_PCIE_HPA_AXI_SLAVE 0x03000000
>>> +#define CDNS_PCIE_HPA_AXI_MASTER 0x03002000
>>> +
>>> +/* Root Port register base address */
>>> +#define CDNS_PCIE_HPA_RP_BASE 0x0
>>> +
>>> +#define CDNS_PCIE_HPA_LM_ID 0x1420
>>> +
>>> +/* Endpoint Function BARs */
>>> +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG(bar, fn) \
>>> + (((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(fn) : \
>>> + CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG1(fn))
>>> +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(pfn) (0x4000 * (pfn))
>>> +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG1(pfn) ((0x4000 * (pfn))
>+
>>0x04)
>>> +#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG(bar, fn) \
>>> + (((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(fn) : \
>>> + CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG1(fn))
>>> +#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(vfn) ((0x4000 * (vfn))
>+
>>0x08)
>>> +#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG1(vfn) ((0x4000 * (vfn))
>+
>>0x0C)
>>> +#define
>>CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(f) \
>>> + (GENMASK(9, 4) << ((f) * 10))
>>> +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \
>>> + (((a) << (4 + ((b) * 10))) &
>>(CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)))
>>> +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(f) \
>>> + (GENMASK(3, 0) << ((f) * 10))
>>> +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \
>>> + (((c) << ((b) * 10)) &
>>(CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)))
>>> +
>>> +/* Endpoint Function Configuration Register */
>>> +#define CDNS_PCIE_HPA_LM_EP_FUNC_CFG 0x02C0
>>> +
>>> +/* Root Complex BAR Configuration Register */
>>> +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG 0x14
>>> +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE_MASK
>>GENMASK(9, 4)
>>> +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE(a) \
>>> +
>> FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE_MA
>>SK, a)
>>> +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL_MASK
>>GENMASK(3, 0)
>>> +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL(c) \
>>> + FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL_MASK, c)
>>> +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE_MASK
>>GENMASK(19, 14)
>>> +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE(a) \
>>> +
>> FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE_MA
>>SK, a)
>>> +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL_MASK
>>GENMASK(13, 10)
>>> +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL(c) \
>>> + FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL_MASK, c)
>>> +
>>> +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE
>>BIT(20)
>>> +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS
>>BIT(21)
>>> +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_ENABLE BIT(22)
>>> +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_32BITS BIT(23)
>>> +
>>> +/* BAR control values applicable to both Endpoint Function and Root
>>Complex */
>>> +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED 0x0
>>> +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS 0x3
>>> +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS 0x1
>>> +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS
>>0x9
>>> +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS 0x5
>>> +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS
>>0xD
>>> +
>>> +#define HPA_LM_RC_BAR_CFG_CTRL_DISABLED(bar) \
>>> + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED << ((bar) *
>>10))
>>> +#define HPA_LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \
>>> + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS << ((bar) *
>>10))
>>> +#define HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \
>>> + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS << ((bar)
>>* 10))
>>> +#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \
>>> +
>> (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS <<
>>((bar) * 10))
>>> +#define HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \
>>> + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS << ((bar)
>>* 10))
>>> +#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \
>>> +
>> (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS <<
>>((bar) * 10))
>>> +#define HPA_LM_RC_BAR_CFG_APERTURE(bar, aperture) \
>>> + (((aperture) - 7) << ((bar) * 10))
>>> +
>>> +#define CDNS_PCIE_HPA_LM_PTM_CTRL 0x0520
>>> +#define CDNS_PCIE_HPA_LM_TPM_CTRL_PTMRSEN BIT(17)
>>> +
>>> +/* Root Port Registers PCI config space for root port function */
>>> +#define CDNS_PCIE_HPA_RP_CAP_OFFSET 0xC0
>>> +
>>> +/* Region r Outbound AXI to PCIe Address Translation Register 0 */
>>> +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r) (0x1010 +
>>((r) & 0x1F) * 0x0080)
>>> +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS_MASK
>>GENMASK(5, 0)
>>> +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \
>>> + (((nbits) - 1) &
>>CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
>>> +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK
>>GENMASK(23, 16)
>>> +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \
>>> +
>> FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN_M
>>ASK, devfn)
>>> +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS_MASK
>>GENMASK(31, 24)
>>> +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS(bus) \
>>> +
>> FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS_MASK
>>, bus)
>>> +
>>> +/* Region r Outbound AXI to PCIe Address Translation Register 1 */
>>> +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r) (0x1014 +
>>((r) & 0x1F) * 0x0080)
>>> +
>>> +/* Region r Outbound PCIe Descriptor Register */
>>> +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r) (0x1008 + ((r)
>>& 0x1F) * 0x0080)
>>> +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK
>>GENMASK(28, 24)
>>> +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MEM \
>>> + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK,
>>0x0)
>>> +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_IO \
>>> + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK,
>>0x2)
>>> +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 \
>>> + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK,
>>0x4)
>>> +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 \
>>> + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK,
>>0x5)
>>> +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG \
>>> + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK,
>>0x10)
>>> +
>>> +/* Region r Outbound PCIe Descriptor Register */
>>> +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r) (0x100C + ((r) &
>>0x1F) * 0x0080)
>>> +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS_MASK
>>GENMASK(31, 24)
>>> +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(bus) \
>>> + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS_MASK,
>>bus)
>>> +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK
>>GENMASK(23, 16)
>>> +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(devfn) \
>>> + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK,
>>devfn)
>>> +
>>> +#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r) (0x1018 + ((r) &
>>0x1F) * 0x0080)
>>> +#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS BIT(26)
>>> +#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN BIT(25)
>>> +
>>> +/* Region r AXI Region Base Address Register 0 */
>>> +#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r) (0x1000 + ((r)
>&
>>0x1F) * 0x0080)
>>> +#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK
>>GENMASK(5, 0)
>>> +#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \
>>> + (((nbits) - 1) &
>>CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
>>> +
>>> +/* Region r AXI Region Base Address Register 1 */
>>> +#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r) (0x1004 + ((r)
>&
>>0x1F) * 0x0080)
>>> +
>>> +/* Root Port BAR Inbound PCIe to AXI Address Translation Register */
>>> +#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0(bar) (((bar) *
>>0x0008))
>>> +#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS_MASK
>>GENMASK(5, 0)
>>> +#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \
>>> + (((nbits) - 1) & CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS_MASK)
>>> +#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR1(bar) (0x04 +
>((bar)
>>* 0x0008))
>>> +
>>> +/* AXI link down register */
>>> +#define CDNS_PCIE_HPA_AT_LINKDOWN 0x04
>>> +
>>> +/*
>>> + * Physical Layer Configuration Register 0
>>> + * This register contains the parameters required for functional setup
>>> + * of Physical Layer.
>>> + */
>>> +#define CDNS_PCIE_HPA_PHY_LAYER_CFG0 0x0400
>>> +#define CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK
>GENMASK(26,
>>24)
>>> +#define CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY(delay) \
>>> + FIELD_PREP(CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK,
>>delay)
>>> +#define CDNS_PCIE_HPA_LINK_TRNG_EN_MASK GENMASK(27, 27)
>>> +
>>> +#define CDNS_PCIE_HPA_PHY_DBG_STS_REG0 0x0420
>>> +
>>> +#define CDNS_PCIE_HPA_RP_MAX_IB 0x3
>>> +#define CDNS_PCIE_HPA_MAX_OB 15
>>> +
>>> +/* Endpoint Function BAR Inbound PCIe to AXI Address Translation
>Register
>>*/
>>> +#define CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) (((fn) *
>>0x0040) + ((bar) * 0x0008))
>>> +#define CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) (0x4 +
>((fn)
>>* 0x0040) + ((bar) * 0x0008))
>>> +
>>> +/* Miscellaneous offsets definitions */
>>> +#define CDNS_PCIE_HPA_TAG_MANAGEMENT 0x0
>>> +#define CDNS_PCIE_HPA_SLAVE_RESP 0x100
>>> +
>>> +#define I_ROOT_PORT_REQ_ID_REG 0x141c
>>> +#define LM_HAL_SBSA_CTRL 0x1170
>>> +
>>> +#define I_PCIE_BUS_NUMBERS (CDNS_PCIE_HPA_RP_BASE +
>>0x18)
>>> +#endif /* _PCIE_CADENCE_HPA_REGS_H */
>>> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h
>>b/drivers/pci/controller/cadence/pcie-cadence.h
>>> index 79df86117fde..ddfc44f8d3ef 100644
>>> --- a/drivers/pci/controller/cadence/pcie-cadence.h
>>> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
>>> @@ -11,6 +11,7 @@
>>> #include <linux/pci-epf.h>
>>> #include <linux/phy/phy.h>
>>> #include "pcie-cadence-lga-regs.h"
>>> +#include "pcie-cadence-hpa-regs.h"
>>>
>>> enum cdns_pcie_rp_bar {
>>> RP_BAR_UNDEFINED = -1,
>>> --
>>> 2.49.0
>>>
>>
>>--
>>மணிவண்ணன் சதாசிவம்
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